Since all chips have the same address, so the capacity of word will be increased.

Explanation:

To understand the answer to this question, we need to have a basic understanding of how memory chips are organized and how their address buses work.

Memory Chip Organization:
Memory chips are organized into rows and columns, forming a rectangular grid. Each cell in the grid stores a single bit of data. The number of rows and columns determines the size of the memory chip. For example, a 16 ✖ 4 memory chip has 16 rows and 4 columns, resulting in a total of 64 cells.

Address Bus:
The address bus is used to specify the location of the desired data in the memory chip. The number of address lines determines the maximum number of addressable locations in the memory chip. For example, if a memory chip has 4 address lines, it can address up to 2^4 = 16 locations.

Connecting Memory Chips:
In the given scenario, four memory chips of 16 ✖ 4 size have their address buses connected together. This means that the address buses of all four memory chips are joined into a single bus.

When multiple memory chips are connected together, the total size of the system is determined by the number of address lines in the address bus. If each memory chip has n address lines, then the combined system will have a total of n address lines.

Determining the Size of the System:
In this case, each memory chip has 4 address lines. Therefore, when the address buses of all four memory chips are connected, the combined system will have a total of 4 address lines.

The number of addressable locations in a memory system is given by 2^n, where n is the number of address lines. In this case, the number of addressable locations is 2^4 = 16.

Since the system has a total of 16 addressable locations, and each location stores 4 bits of data (as each memory chip is of 16 ✖ 4 size), the size of the system is determined as 16 ✖ 4.

Therefore, the correct answer is option 'C', which states that the system size is 16 ✖ 16.