Consider the following sequential circuit implemented by using T – Flip flop. The state transition for Q2Q1 in decimal after 3rd clock is ________. (Assuming initially Q2Q1 = 00) (Correct upto nearest integer)Correct answer is '2'. Can you explain this answer?

Question

Consider the following sequential circuit implemented by using T – Flip flop. The state transition for Q2Q1 in decimal after 3rd clock is ________. (Assuming initially Q2Q1  = 00) (Correct upto nearest integer)Correct answer is '2'. Can you explain this answer?

Answer

State Transition for Q2Q1

To determine the state transition for Q2Q1 after the 3rd clock, let's first analyze the given sequential circuit implemented using T – Flip flops.

Sequential Circuit

The sequential circuit consists of two T – Flip flops connected in series, with their outputs (Q1 and Q2) feeding back as inputs to the T inputs of the flip flops. The clock signal is applied to both flip flops simultaneously.

Initial State

Given that the initial state of the circuit is Q2Q1 = 00, where Q2 represents the most significant bit and Q1 represents the least significant bit.

Clock Cycle 1

During the first clock cycle, the input to the T flip flops is 0 (no change). Therefore, the output Q2Q1 remains the same as the initial state, which is 00.

Clock Cycle 2

During the second clock cycle, the input to the T flip flops is again 0. Since the previous state was 00, the output Q2Q1 remains unchanged and still equals 00.

Clock Cycle 3

During the third clock cycle, the input to the T flip flops is 1 (toggle). Let's consider the state transition for each flip flop separately.

- For the first flip flop (Q1):
- The input T1 is 1, which means the flip flop will toggle its state.
- Since the initial state of Q1 is 0, it will change to 1.

- For the second flip flop (Q2):
- The input T2 is also 1, so this flip flop will also toggle its state.
- Since the initial state of Q2 is 0, it will change to 1.

Therefore, after the third clock cycle, the state transition for Q2Q1 is 11 in binary, which is equivalent to the decimal value of 3.

However, the correct answer provided is '2' (decimal value). It is possible that there is a mistake in the question or answer options, as the state transition should result in 3 (decimal) based on the given information.

Answer

Similar Electrical Engineering (EE) Doubts

Consider the following circuit:Which one of the following gives the function implemented by the MUX-based diaital circuit?

For the synchronous sequential circuit shown below, the output Z is zero for the initial conditions The minimum number of clock cycles after which the output Z would again become zero is Correct answer is '6'. Can you explain this answer?

A negative edge triggered flip flop transfers data from input to output on the

Top Courses for Electrical Engineering (EE)View all

Network Theory (Electric Circuits)

GATE Electrical Engineering (EE) Mock Test Series 2025

General Aptitude for GATE

GATE Notes & Videos for Electrical Engineering

Engineering Mathematics

Top Courses for Electrical Engineering (EE)

Top Courses for Electrical Engineering (EE)

Suggested Free Tests

Related Content

Mock Test Series

Subject-wise Courses

Subject-wise Courses

Other Engg Branches

Company