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Consider 2 kB direct mapped cache, 64 Byte block size 64 kB main memory and 16 bit word size, CPU access words P, Q, R and S respectively 10 times i.e. (P Q R S). Starting address of first byte of P, Q, R and S is respectively. 
P = A248, Q = CA8A, R = C28A, S = A262
Which of the following is/are true (initially cache is empty) 
  • a)
    Expect for the first time P is always a hit
  • b)
    S is always a hit
  • c)
    Q is replaced every time R is accessed
  • d)
    S and Q remain in the main memory after complete execution.
Correct answer is option 'A,B,C,D'. Can you explain this answer?
Most Upvoted Answer
Consider 2 kB direct mapped cache, 64 Byte block size 64 kB main memor...
Cache line 2kB/64B = 32
∴ Line offset = 5 bit
Bits in Physical address = log2 (Main memory size = log2 (64 kB) = 16 bit)
Physical address format for direct mapped cache

Physical address format for main memory 

  • P and S are in same block of memory physical address
  • Q and S are different block of main memory but mapped to same cache line. 
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Consider 2 kB direct mapped cache, 64 Byte block size 64 kB main memory and 16 bit word size, CPU access words P, Q, R and S respectively 10 times i.e. (P Q R S). Starting address of first byte of P, Q, R and S is respectively.P = A248, Q = CA8A, R = C28A, S = A262Which of the following is/are true (initially cache is empty)a)Expect for the first time P is always a hitb)S is always a hitc)Q is replaced every time R is accessedd)S and Q remain in the main memory after complete execution.Correct answer is option 'A,B,C,D'. Can you explain this answer?
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Consider 2 kB direct mapped cache, 64 Byte block size 64 kB main memory and 16 bit word size, CPU access words P, Q, R and S respectively 10 times i.e. (P Q R S). Starting address of first byte of P, Q, R and S is respectively.P = A248, Q = CA8A, R = C28A, S = A262Which of the following is/are true (initially cache is empty)a)Expect for the first time P is always a hitb)S is always a hitc)Q is replaced every time R is accessedd)S and Q remain in the main memory after complete execution.Correct answer is option 'A,B,C,D'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider 2 kB direct mapped cache, 64 Byte block size 64 kB main memory and 16 bit word size, CPU access words P, Q, R and S respectively 10 times i.e. (P Q R S). Starting address of first byte of P, Q, R and S is respectively.P = A248, Q = CA8A, R = C28A, S = A262Which of the following is/are true (initially cache is empty)a)Expect for the first time P is always a hitb)S is always a hitc)Q is replaced every time R is accessedd)S and Q remain in the main memory after complete execution.Correct answer is option 'A,B,C,D'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider 2 kB direct mapped cache, 64 Byte block size 64 kB main memory and 16 bit word size, CPU access words P, Q, R and S respectively 10 times i.e. (P Q R S). Starting address of first byte of P, Q, R and S is respectively.P = A248, Q = CA8A, R = C28A, S = A262Which of the following is/are true (initially cache is empty)a)Expect for the first time P is always a hitb)S is always a hitc)Q is replaced every time R is accessedd)S and Q remain in the main memory after complete execution.Correct answer is option 'A,B,C,D'. Can you explain this answer?.
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