Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Questions > A 4-bit carry look ahead adder, which adds tw...
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A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only.Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.
- a)4 time units
- b)6 time units
- c)10 time units
- d)12 time units
Correct answer is option 'B'. Can you explain this answer?
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Verified Answer
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is desig...
Let the input carry to the first adder be denoted by C1.
Now, to calculate C2 we need = P1C1 + G1 = 4 gate levels (P1 takes 2 gate levels)
to calculate S1 we need = P1 XOR C1 = 2 + 2 = 4 gate levels.
Since it is a Carry look ahead adder, computing C3 , S2 doesn’t have to wait for carry output C2 from the previous adder as C2, C3 etc will get computed at the same time.
Now,
S2 is computed as = P2 XOR C2 = P2.C2′ + P2′.C2
= P2 (P1.C1 + G1 )’ + P2′ (P1.C1 + G1) [ notice that we are not using the output carry from first adder C2 anywhere here ]
which can be implemented using 4 gate levels.
also C3 can be computed by using 4 gate levels and so on…
so the overall propagation delay is 4 gate level as the outputs at Si , Ci are available at the respective full adders after 4 gate levels = 4 time units.
Most Upvoted Answer
A 4-bit carry look ahead adder, which adds two 4-bit numbers, is desig...
Solution:
Given that, we need to design a 4-bit carry look ahead adder using AND, OR, NOT, NAND, NOR gates only. Let's consider the block diagram of the 4-bit carry look ahead adder.
Block Diagram:
The 4-bit carry look ahead adder consists of three main blocks:
1. Sum block
2. Carry block
3. Final sum and carry generation block
1. Sum block:
The sum block generates the sum of two 4-bit numbers. It can be implemented using XOR gates.
2. Carry block:
The carry block generates the carry for each bit. It can be implemented using AND and OR gates.
3. Final sum and carry generation block:
The final sum and carry generation block generates the final sum and carry for the addition of two 4-bit numbers. It can be implemented using NOR gates.
Propogation Delay:
The worst-case delay of a 2-level AND-OR gate is 3 time units. The carry block has 4 such gates. Therefore, the delay of the carry block is 4 * 3 = 12 time units.
The sum block has 4 XOR gates, each with a delay of 1 time unit. Therefore, the delay of the sum block is 4 * 1 = 4 time units.
The final sum and carry generation block has 2 NOR gates, each with a delay of 2 time units. Therefore, the delay of the final sum and carry generation block is 2 * 2 = 4 time units.
The overall propagation delay of the 4-bit carry look ahead adder is the sum of the delays of the three blocks.
Overall Propagation Delay = Delay of Carry Block + Delay of Sum Block + Delay of Final Sum and Carry Generation Block
Overall Propagation Delay = 12 + 4 + 4 = 20 time units.
Therefore, the correct option is (B) 6 time units.
Given that, we need to design a 4-bit carry look ahead adder using AND, OR, NOT, NAND, NOR gates only. Let's consider the block diagram of the 4-bit carry look ahead adder.
Block Diagram:
The 4-bit carry look ahead adder consists of three main blocks:
1. Sum block
2. Carry block
3. Final sum and carry generation block
1. Sum block:
The sum block generates the sum of two 4-bit numbers. It can be implemented using XOR gates.
2. Carry block:
The carry block generates the carry for each bit. It can be implemented using AND and OR gates.
3. Final sum and carry generation block:
The final sum and carry generation block generates the final sum and carry for the addition of two 4-bit numbers. It can be implemented using NOR gates.
Propogation Delay:
The worst-case delay of a 2-level AND-OR gate is 3 time units. The carry block has 4 such gates. Therefore, the delay of the carry block is 4 * 3 = 12 time units.
The sum block has 4 XOR gates, each with a delay of 1 time unit. Therefore, the delay of the sum block is 4 * 1 = 4 time units.
The final sum and carry generation block has 2 NOR gates, each with a delay of 2 time units. Therefore, the delay of the final sum and carry generation block is 2 * 2 = 4 time units.
The overall propagation delay of the 4-bit carry look ahead adder is the sum of the delays of the three blocks.
Overall Propagation Delay = Delay of Carry Block + Delay of Sum Block + Delay of Final Sum and Carry Generation Block
Overall Propagation Delay = 12 + 4 + 4 = 20 time units.
Therefore, the correct option is (B) 6 time units.
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A 4-bit carry look ahead adder, which adds two 4-bit numbers, is designed using AND, OR, NOT, NAND, NOR gates only.Assuming that all the inputs are available in both complemented and uncomplemented forms and the delay of each gate is one time unit, what is the overall propagation delay of the adder? Assume that the carry network has been implemented using two-level AND-OR logic.a)4 time unitsb)6 time unitsc)10 time unitsd)12 time unitsCorrect answer is option 'B'. Can you explain this answer?
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