All Courses
Explore Courses UPSC Exam UPSC Test Series Free Notes EduRev Infinity Get the App Login Join for Free
Sign in Open App
Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Questions  >  A processor uses 36 bit physical addresses an... Start Learning for Free
SaveJoin the Discussion on the App
A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows
• Bits 30-31 are used to index into the first level page table
• Bits 21-29 are used to index into the second level page table
• Bits 12-20 are used to index into the third level page table, and
• Bits 0-11 are used as offset within the page.
The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.
  • a)
    20, 20 and 20
  • b)
    24, 24 and 24
  • c)
    24, 24 and 20
  • d)
    25, 25 and 24
Correct answer is option 'D'. Can you explain this answer?
FREE This question is part of
Download PDF Attempt Test
Download PDF Attempt this Test
Verified Answer
A processor uses 36 bit physical addresses and 32 bit virtual addresse...
Virtual address size = 32 bits Physical address size = 36 bits Physical memory size = 2^36 bytes Page frame size = 4K bytes = 2^12 bytes No. of bits for offset (or number of bits required for accessing location within a page frame) = 12. No. of bits required to access physical memory frame = 36 - 12 = 24 So in third level of page table, 24 bits are required to access an entry. 9 bits of virtual address are used to access second level page table entry and size of pages in second level is 4 bytes. So size of second level page table is (2^9)*4 = 2^11 bytes. It means there are (2^36)/(2^11) possible locations to store this page table. Therefore the second page table requires 25 bits to address it. Similarly, the third page table needs 25 bits to address it.
View all questions of this test
Most Upvoted Answer
A processor uses 36 bit physical addresses and 32 bit virtual addresse...
:

- The 12 most significant bits are used as the index into the first level page table
- The next 10 bits are used as the index into the second level page table
- The next 10 bits are used as the index into the third level page table
- The 10 least significant bits are used as the offset within the page frame

Assuming that the page tables are stored in memory, answer the following questions:

1. What is the size of each page frame?
- 4 Kbytes

2. What is the maximum size of physical memory that can be addressed by the processor?
- Since the physical address space is 36 bits, the maximum size of physical memory that can be addressed is 2^36 bytes = 64 GB.

3. What is the maximum size of virtual memory that can be addressed by the processor?
- Since the virtual address space is 32 bits, the maximum size of virtual memory that can be addressed is 2^32 bytes = 4 GB.

4. How many bits are used to index into the first level page table?
- 12 bits

5. How many bits are used to index into the second level page table?
- 10 bits

6. How many bits are used to index into the third level page table?
- 10 bits

7. How many page table entries are required for the first level page table?
- Since the first level page table indexes into the second level page tables, and there are 2^12 possible index values, there are 2^12 page table entries required for the first level page table.

8. How many page table entries are required for the second level page table?
- Since the second level page table indexes into the third level page tables, and there are 2^10 possible index values, there are 2^10 page table entries required for each entry in the first level page table. Therefore, there are (2^10) * (2^12) = 2^22 page table entries required for the second level page table.

9. How many page table entries are required for the third level page table?
- Since the third level page table maps to page frames, and there are 2^10 possible index values, there are 2^10 page table entries required for each entry in the second level page table. Therefore, there are (2^10) * (2^10) * (2^12) = 2^32 page table entries required for the third level page table.

10. What is the total size of all the page tables?
- The size of each page table entry is 4 bytes. Therefore, the total size of all the page tables is:

(2^12 * 4) + (2^22 * 4) + (2^32 * 4) = 16,777,216 + 4,398,046,720 + 17,592,186,044,672 = 17,609,930,784 bytes = 16.4 GB.

Note: This assumes that each page table is fully populated with entries. In reality, many of the entries will be unused and can be optimized away to reduce the overall size of the page tables.
< Previous Question Next Question >
Explore Courses for Computer Science Engineering (CSE) exam

Similar Computer Science Engineering (CSE) Doubts

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 000400000, and a stack page starting at virtual address 0FFFFF000. The amount of memory required for storing the page tables of this process is

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

Top Courses for Computer Science Engineering (CSE)View all

Top Courses for Computer Science Engineering (CSE)

A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer?
Question Description
A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer?.
Solutions for A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE). Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.
Here you can find the meaning of A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer?, a detailed solution for A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer? has been provided alongside types of A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer? theory, EduRev gives you an ample number of questions to practice A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as follows• Bits 30-31 are used to index into the first level page table• Bits 21-29 are used to index into the second level page table• Bits 12-20 are used to index into the third level page table, and• Bits 0-11 are used as offset within the page.The number of bits required for addressing the next level page table (or page frame) in the page table entry of the first, second and third level page tables are respectively.a)20, 20 and 20b)24, 24 and 24c)24, 24 and 20d)25, 25 and 24Correct answer is option 'D'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
Explore Courses for Computer Science Engineering (CSE) exam

Top Courses for Computer Science Engineering (CSE)

Explore Courses

Suggested Free Tests

Signup for Free!
Signup to see your scores go up within 7 days! Learn & Practice with 1000+ FREE Notes, Videos & Tests.
10M+ students study on EduRev
Get App
© EduRev
Education Revolution
Follow Us
Signup to see your scores go up within 7 days!
Access 1000+ FREE Docs, Videos and Tests
Takes less than 10 seconds to signup