The document 4 Bit Parallel Adder And 8 Bit Full Adder: Binary Arithmetic Circuits Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course Digital Electronics.

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Even the full adder is only adding two single bit binary numbers, but full adders may be combined to form parallel adders, which will add two multiâˆ’bit numbers. Parallel adders can be built in several forms to add multiâˆ’bit binary numbers, each bit of the parallel adder using a single full adder circuit. As parallel adder circuits would look quite complex if drawn showing all the individual gates, it is common to replace the full adder schematic diagram with a simplified block diagram version.

Fig 4.1.3 illustrates how a number of full adders can be combined to make a parallel adder, also called a â€˜Ripple Carry Adderâ€™ because of the way that any carry appearing at the carry in input (C_{IN}) or produced when adding any of the 4-bit inputs, â€˜ripplesâ€™ along the adder stages until a final carry out appears at the carry out output (C_{OUT}) of the final full adder for bit A_{3}+B_{3}.

To carry out arithmetic however, it is also necessary to be able to subtract. A further development of the parallel adder is shown in Fig.4.1.4. This is an 8-bit parallel adder/subtractor. This circuit adds in the same way as the adder in Fig. 4.1.3 but subtracts using the twos complement method described in Digital Electronics Module 1.5 (Ones and Twos Complement).

When subtraction is required, the control input is set to logic 1, which causes the bit at any particular B input to be complemented by an XOR gate before being fed to input B of the full adder circuit.

Twos complement subtraction in an 8-bit adder/subtractor requires that the 8-bit number at input B is complemented (inverted) and has 1 added to it, before being added to the 8-bit number at input A. The result of this will be an 8-bit number in twos complement format, i.e. with its value represented by the lower 7 bits (bit 0 to bit 6) and the sign represented by the most significant bit (bit 7). The logic 1 on the control input is therefore also fed to the first carry input of the adder to be included in the addition, which for subtraction is therefore:

** Input A + Input B + 1**

(Here + signifies addition rather than OR)

Alternatively, if addition of A and B is required, then the control input is at logic 0 and number B is fed to the adder without complementing.

How an XOR gate is used here to change the adder into a subtractor by inverting the B inputs can be seen from the truth table for an XOR gate, shown in Table 4.1.3 (in Fig. 4.1.5). Notice that if input A, (used as the CONTROL input) of the XOR gate is at logic 0, then the XOR gate selects input B, but if input A is logic 1, then it selects the inverse of input B (i.e.B).

The 8-bit adder/subtractor illustrated in Fig. 4.1.4 is designed to add or subtract 8âˆ’bit binary numbers using twos complement notation. In this system the most significant bit (bit 7) is not used as part of the numberâ€™s value, it is used to indicate the sign of the number (0 = positive and 1 = negative).

No matter what the word size of a digital system (8-bits 16-bits 32-bits etc.), a given number of bits can only process numbers up to a maximum value that can be held in its designed word length.

During arithmetical operations it is possible that adding two numbers (with either positive or negative values) that are both within the systemâ€™s limit, can produce a result that is too large for the systemâ€™s word length to hold.

For example, in a twos complement adder such as shown in Fig. 4.1.4, when adding either positive or negative 7-bit values, the result could be larger than 7 bits can accommodate. Therefore the result will need to occupy one extra bit, which means that the calculated value will "overflow" into bit eight, losing a major part (128_{10}) of the value and changing the sign of the result.

To overcome this problem, it is necessary first to detect that an overflow problem has occurred, and then to solve it either by using additional circuits or, in computing, by implementing a corrective routine in software.

Fortunately there is a quite simple method for detecting when an overflow occurs. As shown in Fig. 4.1.5 the overflow detection system consists of a single exclusive or (XOR) gate that takes its inputs from the carry in and carry out connections of the bit 7 (sign bit) adder.

When the carry in (C_{IN}) and carry out (C_{OUT}) bits of this adder are examined, it can be seen that if an overflow has occurred C_{IN} and C_{OUT} will be different, but if no overflow has occurred they will be identical.

Table 4.1.4 shows the effect of adding two positive values where the sum is within the range that can be held in 7 bits (â‰¤127_{10}). The result of adding two positive numbers has produced a correct positive result with no carry and no overflow.

Table 4.1.5 shows a twos complement subtraction performed by adding a negative number to a positive number. The result is 3110 (within the range 0 to +127_{10}), the sign bit is 0 indicating positive result, C_{IN} and C_{OUT} are both 1, so no overflow is detected and the carry bit will be discarded.

Table 4.1.6 shows the effect of adding two negative values where the sum is less than +127_{10} therefore a correct negative result of âˆ’73_{10}(in twos complement notation) has been obtained. Both C_{IN} and C_{OUT} are logic 1 and no overflow will be signalled. As only 8âˆ’bit calculations are being considered, the carry will be discarded.

When the addition of two positive numbers shown in Table. 4.1.7 results in a sum greater than +127_{10} the sign bit is changed from 0 to 1, incorrectly signifying a negative result. As the â€˜carry inâ€™ from bit 6 to bit 7 is 1 and the â€˜carry outâ€™ from bit 7 into the Carry bit is 0 an overflow is detected indicating an incorrect answer.

Notice that if the result of 10011101_{2} were to be considered as an unsigned binary value, the addition in Table 4.1.7 would be correct (157_{10}). However as the calculation is using twos complement notation, the answer of âˆ’99_{10} must be considered as wrong.

Table 4.1.8 shows that adding two negative values can also produce a change in sign and a wrong twos complement result if it is greater than âˆ’128_{10}. In this case adding âˆ’63_{10} and âˆ’73_{10} should have produced a negative result of âˆ’136_{10} and not +120_{10}. To check this, the correct answer (although still with the wrong sign) could be obtained if, noting that an overflow had occurred, the answer was complemented and 1 added, giving an unsigned binary result of 10001000_{2} which converts to 128 + 8 = 136_{10}. Overflow errors can be corrected, but this would require either some additional electronics or a software action in response to the overflow signal.

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