Interrupt Processing Computer Science Engineering (CSE) Notes | EduRev

Computer Architecture and Organisation (CAO) - Notes & all

Computer Science Engineering (CSE) : Interrupt Processing Computer Science Engineering (CSE) Notes | EduRev

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Interrupt Processing
Interrupt processing within a processor is a facility provided to support the operating system. It allows an application program to be suspended, in order that a variety of interrupt conditions can be serviced and later resumed. 

Interrupts And Exceptions
 An interrupt is generated by a signal from hardware, and it may occur at random times during the execution of a program. An exception is generated from software, and it is provoked by the execution of an instruction. There are two sources of interrupts and two sources of exceptions:

1. Interrupts
Maskable interrupts:
Received on the processor’s INTR pin. The processor does not recognize a maskable interrupt unless the interrupt enable flag (IF) is set.
Nonmaskable interrupts:
Received on the processor’s NMI pin. Recognition of such interrupts cannot be prevented. 
• Processor-detected exceptions:
Results when the processor encounters an error while attempting to execute an instruction. • Programmed exceptions: These are instructions that generate an exception (e.g., INTO, INT3, INT, and BOUND). 

Interrupt Vector Table
 Interrupt processing on the x86 uses the interrupt vector table. Every type of interrupt is assigned a number, and this number is used to index into the interrupt vector table. This table contains 256 32-bit interrupt vectors, which is the address (segment and offset) of the interrupt service routine for that interrupt number.

Interrupt Handling
When an interrupt occurs and is recognized by the processor, a sequence of events takes place: 
1 If the transfer involves a change of privilege level, then the current stack segment register and the current extended stack pointer (ESP) register are pushed onto the stack.
2 The current value of the EFLAGS register is pushed onto the stack.
3 Both the interrupt (IF) and trap (TF) flags are cleared. This disables INTR interrupts and the trap or single-step feature.
4 The current code segment (CS) pointer and the current instruction pointer (IP or EIP) are pushed onto the stack.
5 If the interrupt is accompanied by an error code, then the error code is pushed onto the stack.
6 The interrupt vector contents are fetched and loaded into the CS and IP or EIP registers. Execution continues from the interrupt service routine.

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