PPT: Code Generation | Compiler Design - Computer Science Engineering (CSE) PDF Download

 Page 1


Code Generation
Page 2


Code Generation
Outline
? Code Generation Issues
? Target language Issues
? Addresses in Target Code
? Basic Blocks and Flow Graphs
? Optimizations of Basic Blocks
? A Simple Code Generator
? Peephole optimization
? Register allocation and assignment
? Instruction selection by tree rewriting
Page 3


Code Generation
Outline
? Code Generation Issues
? Target language Issues
? Addresses in Target Code
? Basic Blocks and Flow Graphs
? Optimizations of Basic Blocks
? A Simple Code Generator
? Peephole optimization
? Register allocation and assignment
? Instruction selection by tree rewriting
Introduction
? The final phase of a compiler is code generator
? It receives an intermediate representation (IR) with
supplementary information in symbol table
? Produces a semantically equivalent target program
? Code generator main tasks:
? Instruction selection
? Register allocation and assignment
? Insrtuction ordering
Front
end
Code optimizer
Code
Generator
Page 4


Code Generation
Outline
? Code Generation Issues
? Target language Issues
? Addresses in Target Code
? Basic Blocks and Flow Graphs
? Optimizations of Basic Blocks
? A Simple Code Generator
? Peephole optimization
? Register allocation and assignment
? Instruction selection by tree rewriting
Introduction
? The final phase of a compiler is code generator
? It receives an intermediate representation (IR) with
supplementary information in symbol table
? Produces a semantically equivalent target program
? Code generator main tasks:
? Instruction selection
? Register allocation and assignment
? Insrtuction ordering
Front
end
Code optimizer
Code
Generator
Issues in the Design of Code
Generator
? The most important criterion is that it produces correct
code
? Input to the code generator
? IR + Symbol table
? We assume front end produces low-level IR, i.e. values of
names in it can be directly manipulated by the machine
instructions.
? Syntactic and semantic errors have been already detected
? The target program
? Common target architectures are: RISC, CISC and Stack
based machines
? In this chapter we use a very simple RISC-like computer with
addition of some CISC-like addressing modes
Page 5


Code Generation
Outline
? Code Generation Issues
? Target language Issues
? Addresses in Target Code
? Basic Blocks and Flow Graphs
? Optimizations of Basic Blocks
? A Simple Code Generator
? Peephole optimization
? Register allocation and assignment
? Instruction selection by tree rewriting
Introduction
? The final phase of a compiler is code generator
? It receives an intermediate representation (IR) with
supplementary information in symbol table
? Produces a semantically equivalent target program
? Code generator main tasks:
? Instruction selection
? Register allocation and assignment
? Insrtuction ordering
Front
end
Code optimizer
Code
Generator
Issues in the Design of Code
Generator
? The most important criterion is that it produces correct
code
? Input to the code generator
? IR + Symbol table
? We assume front end produces low-level IR, i.e. values of
names in it can be directly manipulated by the machine
instructions.
? Syntactic and semantic errors have been already detected
? The target program
? Common target architectures are: RISC, CISC and Stack
based machines
? In this chapter we use a very simple RISC-like computer with
addition of some CISC-like addressing modes
complexity of mapping
? the level of the IR
? the nature of the instruction-set architecture
? the desired quality of the generated code.
x=y+z
LD R0, y
ADD R0, R0, z
ST x, R0
a=b+c
d=a+e
LD R0, b
ADD R0, R0, c
ST a, R0
LD R0, a
ADD R0, R0, e
ST d, R0