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Parallel Adders

Even the full adder is only adding two single bit binary numbers, but full adders may be combined to form parallel adders, which will add two multi−bit numbers. Parallel adders can be built in several forms to add multi−bit binary numbers, each bit of the parallel adder using a single full adder circuit. As parallel adder circuits would look quite complex if drawn showing all the individual gates, it is common to replace the full adder schematic diagram with a simplified block diagram version.

 

4 Bit Parallel Adder

Fig 4.1.3 illustrates how a number of full adders can be combined to make a parallel adder, also called a ‘Ripple Carry Adder’ because of the way that any carry appearing at the carry in input (CIN) or produced when adding any of the 4-bit inputs, ‘ripples’ along the adder stages until a final carry out appears at the carry out output (COUT) of the final full adder for bit A3+B3.

 

                        4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE)

 

8 Bit Twos Complement Adder/Subtractor

To carry out arithmetic however, it is also necessary to be able to subtract. A further development of the parallel adder is shown in Fig.4.1.4. This is an 8-bit parallel adder/subtractor. This circuit adds in the same way as the adder in Fig. 4.1.3 but subtracts using the twos complement method described in Digital Electronics Module 1.5 (Ones and Twos Complement).

When subtraction is required, the control input is set to logic 1, which causes the bit at any particular B input to be complemented by an XOR gate before being fed to input B of the full adder circuit.

Twos complement subtraction in an 8-bit adder/subtractor requires that the 8-bit number at input B is complemented (inverted) and has 1 added to it, before being added to the 8-bit number at input A. The result of this will be an 8-bit number in twos complement format, i.e. with its value represented by the lower 7 bits (bit 0 to bit 6) and the sign represented by the most significant bit (bit 7). The logic 1 on the control input is therefore also fed to the first carry input of the adder to be included in the addition, which for subtraction is therefore:

                                                 Input A + Input B + 1

                               (Here + signifies addition rather than OR)

Alternatively, if addition of A and B is required, then the control input is at logic 0 and number B is fed to the adder without complementing.

 

                4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE)

 

Adder/Subtractor Control

How an XOR gate is used here to change the adder into a subtractor by inverting the B inputs can be seen from the truth table for an XOR gate, shown in Table 4.1.3 (in Fig. 4.1.5). Notice that if input A, (used as the CONTROL input) of the XOR gate is at logic 0, then the XOR gate selects input B, but if input A is logic 1, then it selects the inverse of input B (i.e.B).

                 4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE)

 

Twos Complement Overflow

The 8-bit adder/subtractor illustrated in Fig. 4.1.4 is designed to add or subtract 8−bit binary numbers using twos complement notation. In this system the most significant bit (bit 7) is not used as part of the number’s value, it is used to indicate the sign of the number (0 = positive and 1 = negative).

No matter what the word size of a digital system (8-bits 16-bits 32-bits etc.), a given number of bits can only process numbers up to a maximum value that can be held in its designed word length.

During arithmetical operations it is possible that adding two numbers (with either positive or negative values) that are both within the system’s limit, can produce a result that is too large for the system’s word length to hold.

For example, in a twos complement adder such as shown in Fig. 4.1.4, when adding either positive or negative 7-bit values, the result could be larger than 7 bits can accommodate. Therefore the result will need to occupy one extra bit, which means that the calculated value will "overflow" into bit eight, losing a major part (12810) of the value and changing the sign of the result.

To overcome this problem, it is necessary first to detect that an overflow problem has occurred, and then to solve it either by using additional circuits or, in computing, by implementing a corrective routine in software.

Fortunately there is a quite simple method for detecting when an overflow occurs. As shown in Fig. 4.1.5 the overflow detection system consists of a single exclusive or (XOR) gate that takes its inputs from the carry in and carry out connections of the bit 7 (sign bit) adder.

When the carry in (CIN) and carry out (COUT) bits of this adder are examined, it can be seen that if an overflow has occurred CIN and COUT will be different, but if no overflow has occurred they will be identical.

 

Adding Two Positive (In Range) Numbers

Table 4.1.4 shows the effect of adding two positive values where the sum is within the range that can be held in 7 bits (≤12710). The result of adding two positive numbers has produced a correct positive result with no carry and no overflow.

 

      4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE)

 

Twos Complement Subtraction

Table 4.1.5 shows a twos complement subtraction performed by adding a negative number to a positive number. The result is 3110 (within the range 0 to +12710), the sign bit is 0 indicating positive result, CIN and COUT are both 1, so no overflow is detected and the carry bit will be discarded.

 

      4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE)

 

Adding Twos Complement Negative Numbers

Table 4.1.6 shows the effect of adding two negative values where the sum is less than +12710 therefore a correct negative result of −7310(in twos complement notation) has been obtained. Both CIN and COUT are logic 1 and no overflow will be signalled. As only 8−bit calculations are being considered, the carry will be discarded.

       4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE)

 

 

Out of Range Result Causes Overflow

When the addition of two positive numbers shown in Table. 4.1.7 results in a sum greater than +12710 the sign bit is changed from 0 to 1, incorrectly signifying a negative result.  As the ‘carry in’ from bit 6 to bit 7 is 1 and the ‘carry out’ from bit 7 into the Carry bit is 0 an overflow is detected indicating an incorrect answer.

 

Notice that if the result of 100111012 were to be considered as an unsigned binary value, the addition in Table 4.1.7 would be correct (15710). However as the calculation is using twos complement notation, the answer of −9910 must be considered as wrong.

       4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE)

 

Out of Range Addition of Negative Values

Table 4.1.8 shows that adding two negative values can also produce a change in sign and a wrong twos complement result if it is greater than −12810. In this case adding −6310 and −7310 should have produced a negative result of −13610 and not +12010. To check this, the correct answer (although still with the wrong sign) could be obtained if, noting that an overflow had occurred, the answer was complemented and 1 added, giving an unsigned binary result of 100010002 which converts to 128 + 8 = 13610. Overflow errors can be corrected, but this would require either some additional electronics or a software action in response to the overflow signal.

 

       4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE) 

The document 4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits | Analog and Digital Electronics - Electrical Engineering (EE) is a part of the Electrical Engineering (EE) Course Analog and Digital Electronics.
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FAQs on 4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits - Analog and Digital Electronics - Electrical Engineering (EE)

1. What is a 4-Bit Parallel Adder?
Ans. A 4-bit parallel adder is a digital circuit that can add two 4-bit binary numbers together. It performs addition by adding each corresponding pair of bits from the two numbers, along with any carry from the previous bit. The result is a sum of the two numbers, represented in binary form.
2. How does a 4-Bit Parallel Adder work?
Ans. A 4-bit parallel adder consists of four full adders connected in parallel. Each full adder takes in two input bits, along with a carry input from the previous full adder. It produces a sum output bit and a carry output bit. These full adders are cascaded together to add each corresponding pair of bits from the two 4-bit numbers. The carry output from one full adder is connected to the carry input of the next full adder, ensuring that any carry is propagated through the circuit.
3. What is an 8-Bit Full Adder?
Ans. An 8-bit full adder is a digital circuit that can add two 8-bit binary numbers together. Similar to a 4-bit parallel adder, it uses full adders to perform the addition operation. However, in this case, there are eight full adders connected in parallel to handle the 8-bit numbers.
4. How do you design an 8-Bit Full Adder circuit?
Ans. To design an 8-bit full adder circuit, you would need to cascade eight full adders together. Each full adder takes in three inputs: two bits from the two 8-bit numbers being added and a carry input from the previous full adder. It produces a sum output bit and a carry output bit. The carry output of each full adder is connected to the carry input of the next full adder, ensuring the correct addition of all bits. The sum outputs of each full adder form the final 8-bit sum of the two numbers.
5. What are the applications of Binary Arithmetic Circuits?
Ans. Binary arithmetic circuits, such as the 4-bit parallel adder and 8-bit full adder, have various applications in digital systems. Some common applications include: - Arithmetic calculations in computer processors and calculators. - Digital signal processing for audio and video processing. - Error detection and correction in communication systems. - Data encryption and decryption algorithms. - Binary-coded decimal (BCD) arithmetic for decimal calculations in digital systems.
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