A full adder adds two single-bit binary numbers, but multiple full adders can be combined to form parallel adders, which add multi-bit numbers. These adders are built using multiple full adders, each handling a single bit of the numbers being added.
Since parallel adder circuits can be complex when drawn with all individual gates, they are commonly represented using simplified block diagrams.
Key Points from Fig. 4.1.3:
Fig. 4.1.4 extends the 4-bit design to an 8-bit adder/subtractor.
Key Observations from Fig. 4.1.4:
Fig. 4.1.5 contains the truth table for an XOR gate, explaining how it switches between addition and subtraction.
The XOR gate takes two inputs:
Thus, the XOR gate acts as a switch, allowing the adder to function as a subtractor.
1. 8-bit Adder/Subtractor:
2. Limitations of Word Size:
3. Overflow in Arithmetic Operations:
4. Effect of Overflow:
5. Overflow Detection:
6. Corrective Measures:
Table 4.1.4 shows the effect of adding two positive values where the sum is within the range that can be held in 7 bits (≤12710). The result of adding two positive numbers has produced a correct positive result with no carry and no overflow.
Table 4.1.5 shows a twos complement subtraction performed by adding a negative number to a positive number. The result is 3110 (within the range 0 to +12710), the sign bit is 0 indicating positive result, CIN and COUT are both 1, so no overflow is detected and the carry bit will be discarded.
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4-Bit Parallel Adder & 8-Bit Full Adder: Binary Arithmetic Circuits
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Table 4.1.6 shows the effect of adding two negative values where the sum is less than +12710 therefore a correct negative result of −7310(in twos complement notation) has been obtained. Both CIN and COUT are logic 1 and no overflow will be signalled. As only 8−bit calculations are being considered, the carry will be discarded.
When the addition of two positive numbers shown in Table. 4.1.7 results in a sum greater than +12710 the sign bit is changed from 0 to 1, incorrectly signifying a negative result. As the ‘carry in’ from bit 6 to bit 7 is 1 and the ‘carry out’ from bit 7 into the Carry bit is 0 an overflow is detected indicating an incorrect answer.
Notice that if the result of 100111012 were to be considered as an unsigned binary value, the addition in Table 4.1.7 would be correct (15710). However as the calculation is using twos complement notation, the answer of −9910 must be considered as wrong.
Table 4.1.8 shows that adding two negative values can also produce a change in sign and a wrong twos complement result if it is greater than −12810. In this case adding −6310 and −7310 should have produced a negative result of −13610 and not +12010. To check this, the correct answer (although still with the wrong sign) could be obtained if, noting that an overflow had occurred, the answer was complemented and 1 added, giving an unsigned binary result of 100010002 which converts to 128 + 8 = 13610. Overflow errors can be corrected, but this would require either some additional electronics or a software action in response to the overflow signal.
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1. What is a 4-bit parallel adder and how does it work? | ![]() |
2. How does an 8-bit two's complement adder/subtractor function? | ![]() |
3. What is the role of the adder/subtractor control in an 8-bit adder/subtractor circuit? | ![]() |
4. How can overflow occur in a two's complement addition, and how is it detected? | ![]() |
5. What are the advantages of using parallel adders over serial adders? | ![]() |