All questions of Digital Logic for Computer Science Engineering (CSE) Exam
An n stage ripple counter can count up to- a)2n
- b)2n - 1
- c)n
- d)2n-1
Correct answer is option 'B'. Can you explain this answer?
An n stage ripple counter can count up to
a)
2n
b)
2n - 1
c)
n
d)
2n-1
|
Sanvi Kapoor answered |
An n stage ripple counter can count up to the binary value represented by the n-bits.
= 2n - 1
= 2n - 1
A positive AND gate is also a negative
- a)NAND gate
- b)OR gate
- c)AND gate
- d)NOR gate
Correct answer is option 'B'. Can you explain this answer?
A positive AND gate is also a negative
a)
NAND gate
b)
OR gate
c)
AND gate
d)
NOR gate
|
Niharika Ahuja answered |
Explanation:
A positive AND gate is a logic gate that produces a HIGH output only when all of its inputs are HIGH. It can be represented by the Boolean expression A.B.
On the other hand, a negative OR gate is a logic gate that produces a LOW output only when all of its inputs are LOW. It can be represented by the Boolean expression A+B.
Now, let's see how a positive AND gate is equivalent to a negative OR gate.
1. NAND gate is not the answer:
A NAND gate is a negative AND gate, which means it produces a LOW output when all of its inputs are HIGH. It can be represented by the Boolean expression A.B. Therefore, a NAND gate is not equivalent to a positive AND gate.
2. AND gate is not the answer:
An AND gate is a positive AND gate, which means it produces a HIGH output only when all of its inputs are HIGH. It can be represented by the Boolean expression A.B. Therefore, an AND gate is the same as a positive AND gate, not a negative OR gate.
3. NOR gate is not the answer:
A NOR gate is a negative OR gate, which means it produces a LOW output only when any of its inputs are HIGH. It can be represented by the Boolean expression A+B. Therefore, a NOR gate is not equivalent to a positive AND gate.
4. OR gate is the answer:
An OR gate is a positive OR gate, which means it produces a HIGH output when any of its inputs are HIGH. It can be represented by the Boolean expression A+B. By using De Morgan's law, we can write the Boolean expression for a negative OR gate as (A.B)'. This is the same as the Boolean expression for a positive AND gate. Therefore, an OR gate is equivalent to a positive AND gate.
Conclusion:
Hence, the correct answer is option B - OR gate.
A positive AND gate is a logic gate that produces a HIGH output only when all of its inputs are HIGH. It can be represented by the Boolean expression A.B.
On the other hand, a negative OR gate is a logic gate that produces a LOW output only when all of its inputs are LOW. It can be represented by the Boolean expression A+B.
Now, let's see how a positive AND gate is equivalent to a negative OR gate.
1. NAND gate is not the answer:
A NAND gate is a negative AND gate, which means it produces a LOW output when all of its inputs are HIGH. It can be represented by the Boolean expression A.B. Therefore, a NAND gate is not equivalent to a positive AND gate.
2. AND gate is not the answer:
An AND gate is a positive AND gate, which means it produces a HIGH output only when all of its inputs are HIGH. It can be represented by the Boolean expression A.B. Therefore, an AND gate is the same as a positive AND gate, not a negative OR gate.
3. NOR gate is not the answer:
A NOR gate is a negative OR gate, which means it produces a LOW output only when any of its inputs are HIGH. It can be represented by the Boolean expression A+B. Therefore, a NOR gate is not equivalent to a positive AND gate.
4. OR gate is the answer:
An OR gate is a positive OR gate, which means it produces a HIGH output when any of its inputs are HIGH. It can be represented by the Boolean expression A+B. By using De Morgan's law, we can write the Boolean expression for a negative OR gate as (A.B)'. This is the same as the Boolean expression for a positive AND gate. Therefore, an OR gate is equivalent to a positive AND gate.
Conclusion:
Hence, the correct answer is option B - OR gate.
Let X and Y be the input and Z be the output of a AND gate. The value of Z is given by
- a)X + Y
- b)
- c)X - Y
- d)
Correct answer is option 'B'. Can you explain this answer?
Let X and Y be the input and Z be the output of a AND gate. The value of Z is given by
a)
X + Y
b)
c)
X - Y
d)
|
Ananya Kumari answered |
Let x and y be the input and z be the output of a and gate . the value of z is given by
x and y is integers they did negative sign
x- y
x and y is integers they did negative sign
x- y
The quantity 837 in excess-3 BCD code would be represented as- a)1001 0011 0111
- b)1000 0001 1001
- c)1011 0110 1010
- d)1000 0011 0111
Correct answer is option 'C'. Can you explain this answer?
The quantity 837 in excess-3 BCD code would be represented as
a)
1001 0011 0111
b)
1000 0001 1001
c)
1011 0110 1010
d)
1000 0011 0111
|
Avinash Sharma answered |
The quantity 837 is first converted to BCD representation then it is incremented by 3 bit by bit.
Consider the circuit-shown below. Each of the control inputs, C0 through C3, must be tied to a constant, either ‘0’ or '1'.
What are the values of C0 through C3 that would cause F to be the exclusive OR of A and B?- a)(1 ,0, 0 ,1 )
- b)( 0 ,1 ,1 ,1 )
- c)(0, 1,1,0)
- d)(1,1, 1,1)
Correct answer is option 'C'. Can you explain this answer?
Consider the circuit-shown below. Each of the control inputs, C0 through C3, must be tied to a constant, either ‘0’ or '1'.
What are the values of C0 through C3 that would cause F to be the exclusive OR of A and B?
What are the values of C0 through C3 that would cause F to be the exclusive OR of A and B?
a)
(1 ,0, 0 ,1 )
b)
( 0 ,1 ,1 ,1 )
c)
(0, 1,1,0)
d)
(1,1, 1,1)
|
Yash Patel answered |
The output of
‘n’ flip-flop will divid e the clock frequency by a factor of- a)n2
- b)n
- c)2n
- d)log(n)
Correct answer is option 'C'. Can you explain this answer?
‘n’ flip-flop will divid e the clock frequency by a factor of
a)
n2
b)
n
c)
2n
d)
log(n)
|
Tushar Unni answered |
n-fiip-flop divide the clock frequency by a factor of 2n.
The refreshing rate of dynamic RAMs is approximately once in- a)Two micro seconds
- b)Two milli seconds
- c)Fifty milli seconds
- d)Two seconds
Correct answer is option 'B'. Can you explain this answer?
The refreshing rate of dynamic RAMs is approximately once in
a)
Two micro seconds
b)
Two milli seconds
c)
Fifty milli seconds
d)
Two seconds
|
|
Mahi Yadav answered |
The refreshing rate of dynamic RAMs is approximately 2 m sec.
A multiplexer is also known as- a)Coder
- b)Decoder
- c)Data selector
- d)Multivibrator
Correct answer is option 'C'. Can you explain this answer?
A multiplexer is also known as
a)
Coder
b)
Decoder
c)
Data selector
d)
Multivibrator
|
Ravi Singh answered |
In electronics, a multiplexer (or mux; spelled sometimes as multiplexor), also known as a data selector, is a device that selects between several analog or digital input signals and forwards the selected input to a single output line.
The vales of x and y, if (x567)8 + (2yx5)8 = (71 yx)8 is- a)4, 3
- b)3, 3
- c)4, 4
- d)4, 5
Correct answer is option 'A'. Can you explain this answer?
The vales of x and y, if (x567)8 + (2yx5)8 = (71 yx)8 is
a)
4, 3
b)
3, 3
c)
4, 4
d)
4, 5
|
Aman Menon answered |
(x 567)8
(2yx5)8
(71yx)8
x will be 4 and y will be 3.
(2yx5)8
(71yx)8
x will be 4 and y will be 3.
Zero has two representation in- a)Sign magnitude
- b)1 ’s complement
- c)2’s complement
- d)Both (a) and (b)
Correct answer is option 'D'. Can you explain this answer?
Zero has two representation in
a)
Sign magnitude
b)
1 ’s complement
c)
2’s complement
d)
Both (a) and (b)
|
Deepika Choudhary answered |
) One's complement
c) Two's complement
c) Two's complement
Register is a- a)Set of capacitor used to register input instructions in a digital computer.
- b)Set to paper tapes and cards put in a file.
- c)Temporary storage unit within the CPU having dedicated or general purpose use.
- d)Part of the auxiliary memory.
Correct answer is option 'C'. Can you explain this answer?
Register is a
a)
Set of capacitor used to register input instructions in a digital computer.
b)
Set to paper tapes and cards put in a file.
c)
Temporary storage unit within the CPU having dedicated or general purpose use.
d)
Part of the auxiliary memory.
|
Rounak Jain answered |
Register is consists of group of flip flop, with each flip-flop having 1 bit of information. Register acts as a temporary storage. Used for general purpose.
Half-adder is also known as- a)AND gate
- b)NAND gate
- c)NOR gate
- d)EX-OR gate
Correct answer is option 'D'. Can you explain this answer?
Half-adder is also known as
a)
AND gate
b)
NAND gate
c)
NOR gate
d)
EX-OR gate
|
|
Akshara Dasgupta answered |
Half-Adder as X-OR Gate
Half-Adder is a digital circuit which is used to add two binary digits. It has two inputs and two outputs. The two inputs are the binary digits to be added and the two outputs are the sum and carry. Half-Adder can be implemented using logic gates, and it is also known as a basic building block for the addition of binary numbers.
Half-Adder using X-OR Gate
X-OR gate is a logic gate which produces an output of 1 if the two inputs are different and 0 if they are the same. The truth table of X-OR gate is shown below.
| Input 1 | Input 2 | Output |
|---------|---------|--------|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The sum output of the Half-Adder can be obtained by using an X-OR gate. The truth table of the Half-Adder using an X-OR gate is shown below.
| Input 1 | Input 2 | Sum |
|---------|---------|-----|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The carry output of the Half-Adder can be obtained by using an AND gate. The truth table of the Half-Adder using an AND gate is shown below.
| Input 1 | Input 2 | Carry |
|---------|---------|-------|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Conclusion
Hence, from the above explanation, it is clear that the Half-Adder is implemented using an X-OR gate for the sum output and an AND gate for the carry output. Therefore, the correct answer is option D, that is, the Half-Adder is also known as an X-OR gate.
Half-Adder is a digital circuit which is used to add two binary digits. It has two inputs and two outputs. The two inputs are the binary digits to be added and the two outputs are the sum and carry. Half-Adder can be implemented using logic gates, and it is also known as a basic building block for the addition of binary numbers.
Half-Adder using X-OR Gate
X-OR gate is a logic gate which produces an output of 1 if the two inputs are different and 0 if they are the same. The truth table of X-OR gate is shown below.
| Input 1 | Input 2 | Output |
|---------|---------|--------|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The sum output of the Half-Adder can be obtained by using an X-OR gate. The truth table of the Half-Adder using an X-OR gate is shown below.
| Input 1 | Input 2 | Sum |
|---------|---------|-----|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 1 |
| 1 | 1 | 0 |
The carry output of the Half-Adder can be obtained by using an AND gate. The truth table of the Half-Adder using an AND gate is shown below.
| Input 1 | Input 2 | Carry |
|---------|---------|-------|
| 0 | 0 | 0 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
Conclusion
Hence, from the above explanation, it is clear that the Half-Adder is implemented using an X-OR gate for the sum output and an AND gate for the carry output. Therefore, the correct answer is option D, that is, the Half-Adder is also known as an X-OR gate.
Let an an-1 ... a1 a0 be the binary representation of an integer b. The integer b is divisible by 3 if- a)The number of one’s is divisible by 3
- b)The number of one’s divisible by 3, but bof by 9
- c)The number of zeroes is divisible 3
- d)The difference of alternate sum, i.e., (a0,+a2+...) - a1+a3+...) is divided by 3
Correct answer is option 'D'. Can you explain this answer?
Let an an-1 ... a1 a0 be the binary representation of an integer b. The integer b is divisible by 3 if
a)
The number of one’s is divisible by 3
b)
The number of one’s divisible by 3, but bof by 9
c)
The number of zeroes is divisible 3
d)
The difference of alternate sum, i.e., (a0,+a2+...) - a1+a3+...) is divided by 3
|
Saikat Basu answered |
Binary representation of 12 is 110 D
So, (q0 + q2)-{q1 + q3)
= (0 + 1)- ( 0 + 1)
= 1 - 1
= 0
0 is divisible by 3 so, true.
So, (q0 + q2)-{q1 + q3)
= (0 + 1)- ( 0 + 1)
= 1 - 1
= 0
0 is divisible by 3 so, true.
The term Product-of-sum in Boolean algebra means- a)AND function of several OR functions
- b)OR function of several AND functions
- c)OR function of several OR functions
- d)AND function of several AND functions
Correct answer is option 'A'. Can you explain this answer?
The term Product-of-sum in Boolean algebra means
a)
AND function of several OR functions
b)
OR function of several AND functions
c)
OR function of several OR functions
d)
AND function of several AND functions
|
Partho Joshi answered |
Understanding Product-of-Sum in Boolean Algebra
In Boolean algebra, the term "Product-of-Sum" refers to a specific structure of logical expressions involving both AND and OR operations. Let's break it down:
Definition
- Product-of-Sum indicates a combination of multiple OR operations that are then combined using an AND operation.
Structure
- The expression consists of several groups, where each group is an OR function. For example, if we have two variables A and B, the Product-of-Sum form could be represented as:
(A + B)(C + D)
Here, (A + B) and (C + D) are both OR functions.
Operation Explanation
- In the expression above:
- A + B represents an OR operation between A and B.
- C + D represents an OR operation between C and D.
- The overall expression is then multiplied (ANDed) together, hence the term "Product."
Why Option A is Correct
- Option A states "AND function of several OR functions," which accurately describes the Product-of-Sum structure.
- Each term inside the parentheses (the OR operations) is combined using an AND operation, aligning perfectly with the definition.
Contrast with Other Options
- Option B, "OR function of several AND functions," describes a different structure known as Sum-of-Product.
- Other options (C and D) do not correctly represent the Product-of-Sum structure at all.
Conclusion
- Understanding the Product-of-Sum form is crucial for analyzing and simplifying Boolean expressions in computer science and digital logic design.
In Boolean algebra, the term "Product-of-Sum" refers to a specific structure of logical expressions involving both AND and OR operations. Let's break it down:
Definition
- Product-of-Sum indicates a combination of multiple OR operations that are then combined using an AND operation.
Structure
- The expression consists of several groups, where each group is an OR function. For example, if we have two variables A and B, the Product-of-Sum form could be represented as:
(A + B)(C + D)
Here, (A + B) and (C + D) are both OR functions.
Operation Explanation
- In the expression above:
- A + B represents an OR operation between A and B.
- C + D represents an OR operation between C and D.
- The overall expression is then multiplied (ANDed) together, hence the term "Product."
Why Option A is Correct
- Option A states "AND function of several OR functions," which accurately describes the Product-of-Sum structure.
- Each term inside the parentheses (the OR operations) is combined using an AND operation, aligning perfectly with the definition.
Contrast with Other Options
- Option B, "OR function of several AND functions," describes a different structure known as Sum-of-Product.
- Other options (C and D) do not correctly represent the Product-of-Sum structure at all.
Conclusion
- Understanding the Product-of-Sum form is crucial for analyzing and simplifying Boolean expressions in computer science and digital logic design.
Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s complement is- a)1100 0100
- b)1001 1100
- c)10100101
- d)11010101
Correct answer is option 'A'. Can you explain this answer?
Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s complement is
a)
1100 0100
b)
1001 1100
c)
10100101
d)
11010101
|
Navya Choudhary answered |
's complement binary numbers. To find the sum of A and B, we can add them together using binary addition:
1111 1010
+ 0000 1010
-----------
1 0000 0100
The sum of A and B is 10000 0100.
1111 1010
+ 0000 1010
-----------
1 0000 0100
The sum of A and B is 10000 0100.
A computer uses 8 digit mantissa and 2 digit exponent. If a = 0.052 and b = 28 E + 11, then b + a - b will- a)Result in an overflow error
- b)Be 5.28 E+11
- c)Be 0
- d)None
Correct answer is option 'C'. Can you explain this answer?
A computer uses 8 digit mantissa and 2 digit exponent. If a = 0.052 and b = 28 E + 11, then b + a - b will
a)
Result in an overflow error
b)
Be 5.28 E+11
c)
Be 0
d)
None
|
Mrinalini Menon answered |
a = 0.052 and b = 28 E + 1
So, b + a - b will b
a = 0.52 exponent
= -1
b = 28 E + 11 mantissa
= 0,28 exponent
= 13
b + a = 28000000000000 E - 1 + 0.52 E-1
= 280000000000.52 E - 1
With is equal to 28 E + 11
So, b - b = 0
So, b + a - b will b
a = 0.52 exponent
= -1
b = 28 E + 11 mantissa
= 0,28 exponent
= 13
b + a = 28000000000000 E - 1 + 0.52 E-1
= 280000000000.52 E - 1
With is equal to 28 E + 11
So, b - b = 0
A gate in which all inputs must be low to get a high output is called a/an- a)Inverter
- b)NOR gate
- c)AND gate .
- d)NAND gate
Correct answer is option 'B'. Can you explain this answer?
A gate in which all inputs must be low to get a high output is called a/an
a)
Inverter
b)
NOR gate
c)
AND gate .
d)
NAND gate
|
|
Navya Choudhary answered |
Definition of NOR Gate
A NOR gate is a digital logic gate that has two or more inputs and produces an output that is the inverse of the logical NOR of the inputs. In other words, its output is high only when all its inputs are low.
Working of NOR Gate
The NOR gate is a combination of an OR gate and an inverter. When all the inputs to the NOR gate are low, the output of the OR gate is low. Since the output of the OR gate is inverted in the inverter, the output of the NOR gate is high.
Truth Table
The truth table of a NOR gate is as follows:
| Input A | Input B | Output |
|---------|---------|--------|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Applications of NOR Gate
- NOR gates are often used as universal gates, meaning that they can be used to implement any logical function.
- NOR gates are commonly used in digital circuits as a way to check if multiple inputs are low.
- NOR gates are also used in memory circuits, such as in dynamic random-access memory (DRAM).
Conclusion
A gate in which all inputs must be low to get a high output is called a NOR gate. NOR gates are used in digital circuits to check if multiple inputs are low and in memory circuits such as DRAM.
A NOR gate is a digital logic gate that has two or more inputs and produces an output that is the inverse of the logical NOR of the inputs. In other words, its output is high only when all its inputs are low.
Working of NOR Gate
The NOR gate is a combination of an OR gate and an inverter. When all the inputs to the NOR gate are low, the output of the OR gate is low. Since the output of the OR gate is inverted in the inverter, the output of the NOR gate is high.
Truth Table
The truth table of a NOR gate is as follows:
| Input A | Input B | Output |
|---------|---------|--------|
| 0 | 0 | 1 |
| 0 | 1 | 0 |
| 1 | 0 | 0 |
| 1 | 1 | 0 |
Applications of NOR Gate
- NOR gates are often used as universal gates, meaning that they can be used to implement any logical function.
- NOR gates are commonly used in digital circuits as a way to check if multiple inputs are low.
- NOR gates are also used in memory circuits, such as in dynamic random-access memory (DRAM).
Conclusion
A gate in which all inputs must be low to get a high output is called a NOR gate. NOR gates are used in digital circuits to check if multiple inputs are low and in memory circuits such as DRAM.
Identify the logic function performed by the circuit shown in the given figure:
- a)Exclusive OR
- b)Exclusive NOR .
- c)NAND
- d)NOR
Correct answer is option 'B'. Can you explain this answer?
Identify the logic function performed by the circuit shown in the given figure:
a)
Exclusive OR
b)
Exclusive NOR .
c)
NAND
d)
NOR
|
Mansi Shah answered |
Therefore the above circuit performed exclusive NOR gate.
If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be - a)0,17
- b)16,1
- c)1 , 1 6
- d)8 , 8
Correct answer is option 'C'. Can you explain this answer?
If half adders and full adders are implemented using gates, then for the addition of two 17 bit numbers (using minimum gates) the number of half adders and full adders required will be
a)
0,17
b)
16,1
c)
1 , 1 6
d)
8 , 8
|
Rishabh Sharma answered |
As we know that n bit full adder circuit can represent (n + 1) bits sum. In order to represent addition of two 17 bits numbers we require minimum of 16 full adder and 1 half adder.
Note: For the first bit we can use either HA or FA. Hence, for addition of two 17 bit numbers inspire of 17 full adders we can perform the same task using 16 FA and 1 HA.
Hence (c) is the correct option.
Note: For the first bit we can use either HA or FA. Hence, for addition of two 17 bit numbers inspire of 17 full adders we can perform the same task using 16 FA and 1 HA.
Hence (c) is the correct option.
The number of 1s in the binary representation of (3* 4096 + 15*256 + 5* 16 + 3) are - a)8
- b)9
- c)10
- d)12
Correct answer is option 'C'. Can you explain this answer?
The number of 1s in the binary representation of (3* 4096 + 15*256 + 5* 16 + 3) are
a)
8
b)
9
c)
10
d)
12
|
Vaishnavi Dey answered |
3*4096 + 15*256 + 5*16 + 3
As we can see that
As we can see that
Hence, they only remains as same in number of 1’s and when any other number is multiplied by themselves, the number of 1 ’s is only the count of the number of 1 ’s in other multiplicant.
∴ correct option is (c)
Which of the following sets of components is/are sufficient to implement any arbitrary boolean function:
1. XOR gates, NOT gates
2. 2 to 1 multiplexers
3. AND gates, XOR gates
4. Three-input gates that output (A • B) + C for the inputs A . B. and C.- a)2 only
- b)1 and 3
- c)4 only
- d)None of above
Correct answer is option 'A'. Can you explain this answer?
Which of the following sets of components is/are sufficient to implement any arbitrary boolean function:
1. XOR gates, NOT gates
2. 2 to 1 multiplexers
3. AND gates, XOR gates
4. Three-input gates that output (A • B) + C for the inputs A . B. and C.
1. XOR gates, NOT gates
2. 2 to 1 multiplexers
3. AND gates, XOR gates
4. Three-input gates that output (A • B) + C for the inputs A . B. and C.
a)
2 only
b)
1 and 3
c)
4 only
d)
None of above
|
|
Krithika Gupta answered |
2 to 1 multiplexer is a universal circuit.
The number of bits that are typically stored'on each track of a magnetic disk is usually- a)The same
- b)Different
- c)Depend on the program to be stored
- d)Fifty
Correct answer is option 'A'. Can you explain this answer?
The number of bits that are typically stored'on each track of a magnetic disk is usually
a)
The same
b)
Different
c)
Depend on the program to be stored
d)
Fifty
|
|
Ashutosh Pillai answered |
The number of bits that are typically stored on each track of a magnetic disk is usually same because density of storing data into disk is same.
Digital systems are the systems which- a)Handle information in digital form internally
- b)Use analog signals
- c)Manipulate information
- d)Deal with digital information in the external world
Correct answer is option 'A'. Can you explain this answer?
Digital systems are the systems which
a)
Handle information in digital form internally
b)
Use analog signals
c)
Manipulate information
d)
Deal with digital information in the external world
|
|
Abhinandan Abimanayu answered |
Option a is right answer because in digital system every information is handled internally
For what logic gate, the output is complement of the input?- a)NOT
- b)AND
- c)OR
- d)XOR
Correct answer is option 'A'. Can you explain this answer?
For what logic gate, the output is complement of the input?
a)
NOT
b)
AND
c)
OR
d)
XOR
|
Rajesh Mukherjee answered |
By using NOT gate output is complement of input
If a clock with time period 'T' is used with n stage shift register, the output of final stage will be delayed by- a)nTsec
- b)(n -1)Tsec
- c)n/Tsec
- d)(2n-1)Tsec
Correct answer is option 'B'. Can you explain this answer?
If a clock with time period 'T' is used with n stage shift register, the output of final stage will be delayed by
a)
nTsec
b)
(n -1)Tsec
c)
n/Tsec
d)
(2n-1)Tsec
|
Kunal Sen answered |
N stage shift register will take (n - 1) x clock time to show the output of final stage.
The decimal number 0.239 x 213 has the following hexadecimal representation (without normalization and rounding off:- a)0D 24
- b)0D 4D
- c)4D 0D
- d)4D 3D
Correct answer is option 'D'. Can you explain this answer?
The decimal number 0.239 x 213 has the following hexadecimal representation (without normalization and rounding off:
a)
0D 24
b)
0D 4D
c)
4D 0D
d)
4D 3D
|
|
Ayush Basu answered |
The decimal number is 0.239 x 213
We have to find hexadecimal representation without normalization.
Biased exponent = 13 + 64 = 77
Representing 77 in binary (77)10 = (1001101)2
Representing mantissa in binary
senting mantissa in binary (0.239)10 = 0.00111101000101
We have to find hexadecimal representation without normalization.
Biased exponent = 13 + 64 = 77
Representing 77 in binary (77)10 = (1001101)2
Representing mantissa in binary
senting mantissa in binary (0.239)10 = 0.00111101000101
Which of the following boolean algebra statements represent distributive law?- a)(A + B) + C = A + ( B + C)
- b)A . (B + C) = (A . B) + (A . C)
- c)A . (B . C) = (A . B) . C
- d)None of these
Correct answer is option 'B'. Can you explain this answer?
Which of the following boolean algebra statements represent distributive law?
a)
(A + B) + C = A + ( B + C)
b)
A . (B + C) = (A . B) + (A . C)
c)
A . (B . C) = (A . B) . C
d)
None of these
|
Tanishq Yadav answered |
Distributive Law in Boolean Algebra
Definition: Distributive law in boolean algebra is a rule that relates the three basic logical operations AND, OR, and NOT. It states that for any boolean expressions A, B, and C:
- A AND (B OR C) = (A AND B) OR (A AND C)
- A OR (B AND C) = (A OR B) AND (A OR C)
Explanation
The distributive law is an important concept in boolean algebra that is used to simplify boolean expressions. It allows us to distribute the AND and OR operations over each other, which can help in reducing the complexity of the expression. Let's take a look at the given options:
a) (A AND B) OR C = A OR (B OR C)
This is not an example of distributive law. It is actually an example of associative law, which states that the order of grouping of terms in an expression does not affect its value.
b) A AND (B OR C) = (A AND B) OR (A AND C)
This is an example of distributive law. It shows that we can distribute the AND operation over the OR operation.
c) A AND (B AND C) = (A AND B) AND C
This is an example of associative law, which states that the order of grouping of terms in an expression does not affect its value.
d) None of these
This is not a valid option as one of the given options is an example of distributive law.
Conclusion
In conclusion, option B is the correct answer as it represents the distributive law in boolean algebra. The distributive law is an important concept in boolean algebra that helps in simplifying boolean expressions.
Definition: Distributive law in boolean algebra is a rule that relates the three basic logical operations AND, OR, and NOT. It states that for any boolean expressions A, B, and C:
- A AND (B OR C) = (A AND B) OR (A AND C)
- A OR (B AND C) = (A OR B) AND (A OR C)
Explanation
The distributive law is an important concept in boolean algebra that is used to simplify boolean expressions. It allows us to distribute the AND and OR operations over each other, which can help in reducing the complexity of the expression. Let's take a look at the given options:
a) (A AND B) OR C = A OR (B OR C)
This is not an example of distributive law. It is actually an example of associative law, which states that the order of grouping of terms in an expression does not affect its value.
b) A AND (B OR C) = (A AND B) OR (A AND C)
This is an example of distributive law. It shows that we can distribute the AND operation over the OR operation.
c) A AND (B AND C) = (A AND B) AND C
This is an example of associative law, which states that the order of grouping of terms in an expression does not affect its value.
d) None of these
This is not a valid option as one of the given options is an example of distributive law.
Conclusion
In conclusion, option B is the correct answer as it represents the distributive law in boolean algebra. The distributive law is an important concept in boolean algebra that helps in simplifying boolean expressions.
How many full adders are needed to construct an m-bit parallel adder ;- a)m /2
- b)m
- c)m - 1
- d)m + 1
Correct answer is option 'B'. Can you explain this answer?
How many full adders are needed to construct an m-bit parallel adder ;
a)
m /2
b)
m
c)
m - 1
d)
m + 1
|
|
Akshita Chakraborty answered |
We can construct a m-bit parallel adder by,
(i) m-full adders OR
(ii) (m - 1) full adders and one half adder OR
iii) (2m - 1 ) full adders and (n - 1) OR GATES
(i) m-full adders OR
(ii) (m - 1) full adders and one half adder OR
iii) (2m - 1 ) full adders and (n - 1) OR GATES
The advantage of MOS devices over bipolar devices is that- a)It allows higher bit densities and also cost effective
- b)It is easy to fabricate
- c)Its higher-impedance and operational speed
- d)All of these
Correct answer is option 'D'. Can you explain this answer?
The advantage of MOS devices over bipolar devices is that
a)
It allows higher bit densities and also cost effective
b)
It is easy to fabricate
c)
Its higher-impedance and operational speed
d)
All of these
|
|
Maulik Pillai answered |
The advantage of MOS device over bipolar device is, it allows higher bit density and cost effective, easy to fabricate and have higher impedance and operational speed.
The circuit below represents function X{A, B, C, D) as:
- a)∑ ( 3 , 8, 9, 10)
- b)∑ (3 , 8, 10, 14)
- c)
- d)
Correct answer is option 'A'. Can you explain this answer?
The circuit below represents function X{A, B, C, D) as:
a)
∑ ( 3 , 8, 9, 10)
b)
∑ (3 , 8, 10, 14)
c)
d)
|
|
Anoushka Dey answered |
The given circuit represents the implementation of four variable function using 8: 1 MUX here. D as taken as the fourth i/p and A, B, C act as select lines.
A comparison between serial and parallel adder reveals that serial order- a)Is slower
- b)Is faster
- c)Operates at the same speed as parallel adder
- d)Is more complicate
Correct answer is option 'A'. Can you explain this answer?
A comparison between serial and parallel adder reveals that serial order
a)
Is slower
b)
Is faster
c)
Operates at the same speed as parallel adder
d)
Is more complicate
|
|
Ravi Singh answered |
Comparison between serial and parallel adder reveals that serial adder is serial adder is a sequential circuit. A parallel adder is a combinational circuit. In serial adder, propagation delay is less. In parallel adder, propagation delay is present from input carry to output carry.
Which of the following 4-bit numbers equals its 1’s complement?- a)1010
- b)1000
- c)No such number exists
- d)None of these
Correct answer is option 'C'. Can you explain this answer?
Which of the following 4-bit numbers equals its 1’s complement?
a)
1010
b)
1000
c)
No such number exists
d)
None of these
|
Garima Dasgupta answered |
Since in 1 ’s complete every bits get complemented so, no such number exist whose complement is same while in 2’s complement 8 and 0 are exist.
The number of full and half-adder required to add 16-bit numbers is- a)8 half-adders, 8 full-adders
- b)1 half-adder, 15 full-adders
- c)16 half-adders, 0 full-adders
- d)4 half-adders, 12 full-adders
Correct answer is option 'B'. Can you explain this answer?
The number of full and half-adder required to add 16-bit numbers is
a)
8 half-adders, 8 full-adders
b)
1 half-adder, 15 full-adders
c)
16 half-adders, 0 full-adders
d)
4 half-adders, 12 full-adders
|
Kavya Mukherjee answered |
To 16 bits number, 1 half and 15 full address or 16 full address are required.
A single-precision floating point number contains the sequence of bits 100011111 00000000001 000000000000, Information is stored in the following left-to-right order, sign bit, exponent (bias 127) and mantissa. Which of the following representation in decimal is equivalent?- a)231 (1 + 2-12)
- b)(-1) 231(1 + 2-12)
- c)(—1) 2-65 (1 + 2-10)
- d)(-1) 2-96 (1 + 2-11)
Correct answer is option 'D'. Can you explain this answer?
A single-precision floating point number contains the sequence of bits 100011111 00000000001 000000000000, Information is stored in the following left-to-right order, sign bit, exponent (bias 127) and mantissa. Which of the following representation in decimal is equivalent?
a)
231 (1 + 2-12)
b)
(-1) 231(1 + 2-12)
c)
(—1) 2-65 (1 + 2-10)
d)
(-1) 2-96 (1 + 2-11)
|
|
Diya Chauhan answered |
The NAND can function as a NOT gate if- a)Inputs are connected together
- b)Inputs are left open
- c)One input is set to 0
- d)One input is set to 1
Correct answer is option 'A'. Can you explain this answer?
The NAND can function as a NOT gate if
a)
Inputs are connected together
b)
Inputs are left open
c)
One input is set to 0
d)
One input is set to 1
|
|
Ayush Basu answered |
NAND gate work as NOT if inputs are connected together i.e.
The functional difference between SR flip-flop and JK flip-flop is that JK flip-flop- a)Is faster than SR flip-flop
- b)Has a feed back path
- c)Accepts both inputs 1
- d)Does not require external clock
Correct answer is option 'C'. Can you explain this answer?
The functional difference between SR flip-flop and JK flip-flop is that JK flip-flop
a)
Is faster than SR flip-flop
b)
Has a feed back path
c)
Accepts both inputs 1
d)
Does not require external clock
|
|
Rahul Chavan answered |
S-R flip flop gives invalid output when both inputs are 1 while JK flip-flop toggle the previous output when both inputs are 1. Hence it accepts both inputs 1.
Write the minimized expression of the function of three variables that is 1 if the third variable is equal to the OR of the first two variable, 0 otherwise- a)(x+y)+z
- b)
- c)
- d)
Correct answer is option 'C'. Can you explain this answer?
Write the minimized expression of the function of three variables that is 1 if the third variable is equal to the OR of the first two variable, 0 otherwise
a)
(x+y)+z
b)
c)
d)
|
Nisha Das answered |
Constructing the table we have
Hence the required expression is
Hence the required expression is
The inputs of the J-K flip-flop, shown below are:
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will
- a)Toggle
- b)Set
- c)Reset
- d)Not change states
Correct answer is option 'D'. Can you explain this answer?
The inputs of the J-K flip-flop, shown below are:
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will
PRESET = CLEAR = 1; J = K = 0
If a single clock pulse is applied the device will
a)
Toggle
b)
Set
c)
Reset
d)
Not change states
|
|
Vaibhav Patel answered |
To make flip-flop working both preset = apart = 1 Since J = K = 0, so it does not change its state i.e. remains in same state.
The boolean expression A + BC equals - a)
- b)(A + B ) ( A + C )
- c)
- d)None of these
Correct answer is option 'B'. Can you explain this answer?
The boolean expression A + BC equals
a)
b)
(A + B ) ( A + C )
c)
d)
None of these
|
|
Anagha Choudhary answered |
A + BC represents the distributive law which can be expanded as A + BC = (A + B) . (A + C)
If in a shift resistor Q0 is fed back to input the resulting counter is- a)Twisted ring with N : 1 scale
- b)Ring counter with N : 1 scale
- c)Twisted ring with 2 N : 1 scale
- d)Ring counter with 2 N : 1 scale
Correct answer is option 'C'. Can you explain this answer?
If in a shift resistor Q0 is fed back to input the resulting counter is
a)
Twisted ring with N : 1 scale
b)
Ring counter with N : 1 scale
c)
Twisted ring with 2 N : 1 scale
d)
Ring counter with 2 N : 1 scale
|
|
Vaishnavi Dey answered |
Answer:
In a shift resistor, when Q0 is fed back to the input, the resulting counter is a twisted ring counter with a scale of 2N:1.
Explanation:
A shift register is a type of digital circuit that is capable of shifting its data bits one position at a time. It can be used to create a variety of digital circuits, including counters. A shift register counter is a sequential circuit that can count in a specific sequence by shifting the bits through the register.
In a ring counter, the output of the last stage is fed back to the input of the first stage, creating a loop. This allows the bits to circulate through the counter, creating a counting sequence. However, in a regular ring counter, the scale of the counter is N:1, where N is the number of stages or bits in the counter.
When Q0 is fed back to the input of a shift register counter, it creates a twisted ring counter. This means that the output of the first stage is not directly connected to the input of the first stage, but is instead connected to the input of a different stage, creating a twist in the loop. This twist in the loop changes the scale of the counter.
Example:
Let's consider a 4-bit shift register counter. In a regular ring counter, the scale would be 4:1, meaning that it would take four clock cycles for the counter to complete a full cycle. However, when Q0 is fed back to the input, the resulting twisted ring counter has a scale of 2N:1, which in this case is 8:1.
This means that it would take eight clock cycles for the counter to complete a full cycle. The feedback from Q0 to the input effectively doubles the length of the counter sequence.
Therefore, the correct answer is option C - a twisted ring counter with a scale of 2N:1.
In a shift resistor, when Q0 is fed back to the input, the resulting counter is a twisted ring counter with a scale of 2N:1.
Explanation:
A shift register is a type of digital circuit that is capable of shifting its data bits one position at a time. It can be used to create a variety of digital circuits, including counters. A shift register counter is a sequential circuit that can count in a specific sequence by shifting the bits through the register.
In a ring counter, the output of the last stage is fed back to the input of the first stage, creating a loop. This allows the bits to circulate through the counter, creating a counting sequence. However, in a regular ring counter, the scale of the counter is N:1, where N is the number of stages or bits in the counter.
When Q0 is fed back to the input of a shift register counter, it creates a twisted ring counter. This means that the output of the first stage is not directly connected to the input of the first stage, but is instead connected to the input of a different stage, creating a twist in the loop. This twist in the loop changes the scale of the counter.
Example:
Let's consider a 4-bit shift register counter. In a regular ring counter, the scale would be 4:1, meaning that it would take four clock cycles for the counter to complete a full cycle. However, when Q0 is fed back to the input, the resulting twisted ring counter has a scale of 2N:1, which in this case is 8:1.
This means that it would take eight clock cycles for the counter to complete a full cycle. The feedback from Q0 to the input effectively doubles the length of the counter sequence.
Therefore, the correct answer is option C - a twisted ring counter with a scale of 2N:1.
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