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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Questions  >  In DMA transfers, the required signals and ad... Start Learning for Free
 In DMA transfers, the required signals and addresses are given by the
  • a)
    Processor
  • b)
    Device drivers
  • c)
    DMA controllers
  • d)
    The program itself
Correct answer is option 'C'. Can you explain this answer?
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Verified Answer
In DMA transfers, the required signals and addresses are given by thea...
Answer: c
Explanation: The DMA controller acts like a processor for DMA transfers and overlooks the entire process.
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Most Upvoted Answer
In DMA transfers, the required signals and addresses are given by thea...
Explanation:

DMA stands for Direct Memory Access. DMA transfers are used for high-speed data transfer between the memory and the devices. The DMA transfers require signals and addresses to be given for the successful transfer of data. The signals and addresses are given by the DMA controllers.

DMA controllers are special hardware devices that are responsible for managing the DMA transfers. They are responsible for initiating the transfer, controlling the transfer, and completing the transfer. The DMA controllers can transfer data between the memory and devices without the intervention of the processor. This reduces the workload of the processor and improves the system performance.

The DMA controllers require the following signals and addresses for the successful transfer of data:

1. Memory Address: The memory address is the address of the memory location where the data is to be transferred.

2. Device Address: The device address is the address of the device from where the data is to be transferred.

3. Data Bus: The data bus is used for the transfer of data between the memory and the device.

4. Control Signals: The control signals are used to control the transfer of data between the memory and the device.

Conclusion:

Hence, from the above explanation, we can conclude that in DMA transfers, the required signals and addresses are given by the DMA controllers.
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On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.Initialize the address registerInitialize the count to 500LOOP: Load a byte from deviceStore in memory at address given by address registerIncrement the address registerDecrement the countIf count != 0 go to LOOPAssume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.Q. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?

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A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

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