Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Questions > A computer has a256KByte, 4-way set associati...
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A computer has a
256
KByte, 4-way set associative, write back data cache with block size of
32 . The processor sends
Bytes addresses to the cache controller. Each cache tag directory entry contains, in addition to
32
bit address tag,
2 valid bits,
1 modified bit and
1 replacement bit.
The number of bits in the tag field of an address is
256
KByte, 4-way set associative, write back data cache with block size of
32 . The processor sends
Bytes addresses to the cache controller. Each cache tag directory entry contains, in addition to
32
bit address tag,
2 valid bits,
1 modified bit and
1 replacement bit.
The number of bits in the tag field of an address is
- a)11
- b)14
- c)16
- d)27
Correct answer is option 'C'. Can you explain this answer?
Verified Answer
A computer has a256KByte, 4-way set associative, write back data cache...
Total cache size = 256 KB
Cache block size = 32 Bytes
So, number of cache entries = 256 K / 32 = 8 K
Number of sets in cache = 8 K/4 = 2 K as cache is 4-way associative.
So, log(2048) = 11 bits are needed for accessing a set. Inside a set we need to identify the cache entry.
No. of memory block possible = Memory size/Cache block size
So, no. of memory block that can go to a single cache set
Cache block size = 32 Bytes
So, number of cache entries = 256 K / 32 = 8 K
Number of sets in cache = 8 K/4 = 2 K as cache is 4-way associative.
So, log(2048) = 11 bits are needed for accessing a set. Inside a set we need to identify the cache entry.
No. of memory block possible = Memory size/Cache block size
So, no. of memory block that can go to a single cache set
So, we need 16 tag bits along with each cache entry to identify which of the possible 216 blocks is being mapped there.
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Most Upvoted Answer
A computer has a256KByte, 4-way set associative, write back data cache...
The tag field in an address is used to uniquely identify a particular cache block. In this case, we have a 256KByte (kilobyte) data cache with a block size of 32. Let's break down the given information and calculate the number of bits in the tag field.
Cache Size:
256KByte = 256 * 1024 Byte
= 262,144 Byte
Block Size:
32 Byte
Number of Blocks in the Cache:
Cache Size / Block Size
= 262,144 Byte / 32 Byte
= 8,192 Blocks
Set Associativity:
4-way set associative means each set in the cache can hold 4 blocks.
Number of Sets in the Cache:
Number of Blocks / Set Associativity
= 8,192 Blocks / 4
= 2,048 Sets
Tag Directory Entry:
Each cache tag directory entry contains a 32-bit address tag, 2 valid bits, 1 modified bit, and 1 replacement bit.
Number of Bits Required for Valid Bits:
2 valid bits * 2,048 Sets
= 4,096 bits
Number of Bits Required for Modified Bit:
1 modified bit * 2,048 Sets
= 2,048 bits
Number of Bits Required for Replacement Bit:
1 replacement bit * 2,048 Sets
= 2,048 bits
Total Number of Bits Required for Tag Directory Entry:
32-bit address tag + 4,096 bits (valid bits) + 2,048 bits (modified bit) + 2,048 bits (replacement bit)
= 32 + 4,096 + 2,048 + 2,048
= 8,224 bits
Number of Bits in the Tag Field of an Address:
Total Number of Bits in the Tag Directory Entry / Number of Sets in the Cache
= 8,224 bits / 2,048 Sets
= 4 bits
Therefore, the number of bits in the tag field of an address is 4. Hence, option 'C' is the correct answer.
Cache Size:
256KByte = 256 * 1024 Byte
= 262,144 Byte
Block Size:
32 Byte
Number of Blocks in the Cache:
Cache Size / Block Size
= 262,144 Byte / 32 Byte
= 8,192 Blocks
Set Associativity:
4-way set associative means each set in the cache can hold 4 blocks.
Number of Sets in the Cache:
Number of Blocks / Set Associativity
= 8,192 Blocks / 4
= 2,048 Sets
Tag Directory Entry:
Each cache tag directory entry contains a 32-bit address tag, 2 valid bits, 1 modified bit, and 1 replacement bit.
Number of Bits Required for Valid Bits:
2 valid bits * 2,048 Sets
= 4,096 bits
Number of Bits Required for Modified Bit:
1 modified bit * 2,048 Sets
= 2,048 bits
Number of Bits Required for Replacement Bit:
1 replacement bit * 2,048 Sets
= 2,048 bits
Total Number of Bits Required for Tag Directory Entry:
32-bit address tag + 4,096 bits (valid bits) + 2,048 bits (modified bit) + 2,048 bits (replacement bit)
= 32 + 4,096 + 2,048 + 2,048
= 8,224 bits
Number of Bits in the Tag Field of an Address:
Total Number of Bits in the Tag Directory Entry / Number of Sets in the Cache
= 8,224 bits / 2,048 Sets
= 4 bits
Therefore, the number of bits in the tag field of an address is 4. Hence, option 'C' is the correct answer.
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A computer has a256KByte, 4-way set associative, write back data cache with block size of32. The processor sendsBytesaddresses to the cache controller. Each cache tag directory entry contains, in addition to32bit address tag,2valid bits,1modified bit and1replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer?
Question Description
A computer has a256KByte, 4-way set associative, write back data cache with block size of32. The processor sendsBytesaddresses to the cache controller. Each cache tag directory entry contains, in addition to32bit address tag,2valid bits,1modified bit and1replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A computer has a256KByte, 4-way set associative, write back data cache with block size of32. The processor sendsBytesaddresses to the cache controller. Each cache tag directory entry contains, in addition to32bit address tag,2valid bits,1modified bit and1replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A computer has a256KByte, 4-way set associative, write back data cache with block size of32. The processor sendsBytesaddresses to the cache controller. Each cache tag directory entry contains, in addition to32bit address tag,2valid bits,1modified bit and1replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer?.
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