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A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The
processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in
addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.
The number of bits in the tag field of an address is
  • a)
    11
  • b)
    14
  • c)
    16
  • d)
    27
Correct answer is option 'C'. Can you explain this answer?
Most Upvoted Answer
A computer has a 256 KByte, 4-way set associative, write back data cac...

Calculation of the number of bits in the tag field:

- Given cache size = 256 KByte = 256 * 1024 Bytes
- Block size = 32 Bytes
- Number of blocks = Cache size / Block size = 256 * 1024 / 32 = 8192 blocks
- Number of sets = Number of blocks / Associativity = 8192 / 4 = 2048 sets
- Number of bits for set index = log2(Number of sets) = log2(2048) = 11 bits
- Number of bits for block offset = log2(Block size) = log2(32) = 5 bits
- Total number of bits in the address = 32 bits
- Number of bits for tag field = Total number of bits - (Number of bits for set index + Number of bits for block offset)
- Number of bits for tag field = 32 - (11 + 5) = 16 bits

Therefore, the number of bits in the tag field of an address is 16 bits.
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A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. Theprocessor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, inaddition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer?
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A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. Theprocessor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, inaddition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. Theprocessor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, inaddition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. Theprocessor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, inaddition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit.The number of bits in the tag field of an address isa)11b)14c)16d)27Correct answer is option 'C'. Can you explain this answer?.
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