Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Questions  >  A computer has a 256 - KByte, 4-way set assoc... Start Learning for Free
A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory is
  • a)
    160 Kbits
  • b)
    136 Kbits
  • c)
    40 Kbits
  • d)
    32 Kbits
Correct answer is option 'A'. Can you explain this answer?
Verified Answer
A computer has a 256 - KByte, 4-way set associative, write back data c...
Total cache size = 256 KB
Cache block size = 32 Bytes
So, number of cache entries = 256 K / 32 = 8 K
Number of sets in cache = 8 K/4 = 2 K as cache is 4-way associative.
So, log(2048) = 11 bits are needed for accessing a set. Inside a set we need to identify the cache entry.
Total number of distinct cache entries = 232/cache entry size = 232/32 = 227
Out of this 227, each set will be getting only 227/211 = 216 possible distinct cache entries as we use the first 11 bits to
identify a set. So, we need 16 bits to identify a cache entry in a set, which is the number of bits in the tag field.
Size of cache tag directory = Size of tag entry * Number of tag entries
= 16 +(2+1+1) bits (2 valid, 1 modified, 1 replacement as given in question) * 8 K
= 20 * 8 = 160 Kbits
Not needed for this question, still:
Valid bit: Tells if the memory referenced by the cache entry is valid. Initially, when a process is loaded all entries are
invalid. Only when a page is loaded, its entry becomes valid.
Modified bit: When processor writes to a cache location its modified bit is made 1. This information is used when a cache
entry is replaced- entry 0 means no update to main memory needed. Entry 1 means an update is needed.
This question is part of UPSC exam. View all Computer Science Engineering (CSE) courses
Most Upvoted Answer
A computer has a 256 - KByte, 4-way set associative, write back data c...
Given information:
- Cache size = 256 KB
- 4-way set associative
- Block size = 32 bytes
- Address size = 32 bits
- Each cache tag directory entry contains: 2 valid bits, 1 modified bit, and 1 replacement bit

To find: Size of the cache tag directory

Formula to calculate number of sets in a set associative cache:
Number of sets = (Cache size) / (Associativity x Block size)

Number of sets = (256 KB) / (4 x 32 bytes) = 2 K

Number of blocks in each set = Associativity = 4

Therefore, number of total blocks in cache = Number of sets x Associativity = 2 K x 4 = 8 K

Size of each cache block = Block size = 32 bytes = 2^5 bytes

Number of bits needed to represent the byte offset within a block = log2(Block size) = 5 bits

Number of bits needed to represent the set index = log2(Number of sets) = log2(2 K) = 11 bits

Number of bits needed to represent the tag = Address size - (byte offset bits + set index bits) = 32 - (5 + 11) = 16 bits

Size of each cache tag directory entry = tag bits + valid bits + modified bit + replacement bit = 16 + 2 + 1 + 1 = 20 bits

Size of cache tag directory = Total number of blocks x Size of each cache tag directory entry = 8 K x 20 bits = 160 Kbits

Therefore, the correct answer is option A, 160 Kbits.
Explore Courses for Computer Science Engineering (CSE) exam

Similar Computer Science Engineering (CSE) Doubts

Top Courses for Computer Science Engineering (CSE)

A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer?
Question Description
A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer?.
Solutions for A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE). Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.
Here you can find the meaning of A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer?, a detailed solution for A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer? has been provided alongside types of A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer? theory, EduRev gives you an ample number of questions to practice A computer has a 256 - KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The size of the cache tag directory isa)160 Kbitsb)136Kbitsc)40Kbitsd)32KbitsCorrect answer is option 'A'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
Explore Courses for Computer Science Engineering (CSE) exam

Top Courses for Computer Science Engineering (CSE)

Explore Courses
Signup for Free!
Signup to see your scores go up within 7 days! Learn & Practice with 1000+ FREE Notes, Videos & Tests.
10M+ students study on EduRev