Computer Science Engineering (CSE) Exam > Computer Science Engineering (CSE) Questions > Consider a 4-way set associative cache (initi...
Start Learning for Free
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?
- a)3
- b)8
- c)129
- d)216
Correct answer is option 'D'. Can you explain this answer?
Verified Answer
Consider a 4-way set associative cache (initially empty) with total 16...
4 way set associative so 16 block will be divided in 4 sets of 4 blocks each.
We apply(Address mod 4) function to decide set.
All * are misses S1 in the first stage ans S2 in the second.
All * are misses S1 in the first stage ans S2 in the second.
In the second stage 216 is not present in the cache.
So (D) is correct option.
This question is part of UPSC exam. View all Computer Science Engineering (CSE) courses
Most Upvoted Answer
Consider a 4-way set associative cache (initially empty) with total 16...
Solution:
Cache Configuration:
- 4-way set associative
- Total 16 Cache blocks
Main Memory:
- 256 blocks
Request Order:
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155
LRU Replacement Policy:
- Least Recently Used block will be replaced if required
Explanation:
- Initially cache is empty, so the first memory block 0 will not be in cache
- Request for memory block 255, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 1, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 4, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 3, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 8, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 133, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 159, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 216, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 129, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 63, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 8, it is already present in cache (at this point, cache has blocks: 8, 63, 129, 216)
- Request for memory block 48, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 48, 63, 129)
- Request for memory block 32, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 63)
- Request for memory block 73, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 73)
- Request for memory block 92, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 92)
- Request for memory block 155, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 155)
Conclusion:
- As per LRU replacement policy, the Least Recently Used block will be replaced if required
- In the above scenario, if we request for memory block 216 again, it will be present in the cache (as it is used recently), so it will not be replaced
- Hence, the memory block which will NOT be in cache if LRU replacement policy is used is 216 (option D)
Cache Configuration:
- 4-way set associative
- Total 16 Cache blocks
Main Memory:
- 256 blocks
Request Order:
0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155
LRU Replacement Policy:
- Least Recently Used block will be replaced if required
Explanation:
- Initially cache is empty, so the first memory block 0 will not be in cache
- Request for memory block 255, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 1, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 4, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 3, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 8, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 133, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 159, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 216, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 129, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 63, it will not be in cache and will be loaded in an empty cache block
- Request for memory block 8, it is already present in cache (at this point, cache has blocks: 8, 63, 129, 216)
- Request for memory block 48, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 48, 63, 129)
- Request for memory block 32, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 63)
- Request for memory block 73, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 73)
- Request for memory block 92, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 92)
- Request for memory block 155, it will not be in cache and will be loaded in an empty cache block (at this point, cache has blocks: 8, 32, 48, 155)
Conclusion:
- As per LRU replacement policy, the Least Recently Used block will be replaced if required
- In the above scenario, if we request for memory block 216 again, it will be present in the cache (as it is used recently), so it will not be replaced
- Hence, the memory block which will NOT be in cache if LRU replacement policy is used is 216 (option D)
Attention Computer Science Engineering (CSE) Students!
To make sure you are not studying endlessly, EduRev has designed Computer Science Engineering (CSE) study material, with Structured Courses, Videos, & Test Series. Plus get personalized analysis, doubt solving and improvement plans to achieve a great score in Computer Science Engineering (CSE).
|
|
Explore Courses for Computer Science Engineering (CSE) exam
|
|
Similar Computer Science Engineering (CSE) Doubts
Top Courses for Computer Science Engineering (CSE)View all
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer?
Question Description
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer?.
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer?.
Solutions for Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE).
Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.
Here you can find the meaning of Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer?, a detailed solution for Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? has been provided alongside types of Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? theory, EduRev gives you an
ample number of questions to practice Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocksand the request for memory blocks are in the following order:0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155.Which one of the following memory block will NOT be in cache if LRU replacement policy is used?a)3b)8c)129d)216Correct answer is option 'D'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
|
|
Explore Courses for Computer Science Engineering (CSE) exam
|
|
Suggested Free Tests
Signup for Free!
Signup to see your scores go up within 7 days! Learn & Practice with 1000+ FREE Notes, Videos & Tests.
|
© EduRev
|
Education Revolution
|
Follow Us
|
Signup to see your scores
go up within 7 days!
Access 1000+ FREE Docs, Videos and Tests
Takes less than 10 seconds to signup