All Courses
Explore Courses UPSC Exam UPSC Test Series Free Notes EduRev Infinity Get the App Login Join for Free
Sign in Open App
Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Questions  >  How many separate address and data lines are ... Start Learning for Free
SaveJoin the Discussion on the App
How many separate address and data lines are needed for a memory of 8 K × 16 ?
  • a)
    13 address, 3 data lines
  • b)
    13 address, 16 data lines
  • c)
    12 address, 4 data lines
  • d)
    13 address, 4 data lines
Correct answer is option 'B'. Can you explain this answer?
FREE This question is part of
Download PDF Attempt Test
Download PDF Attempt this Test
Most Upvoted Answer
How many separate address and data lines are needed for a memory of 8 ...
For a memory of 8 K, we need 13 address lines and 8 data lines.

Explanation:

- 8 K means 8 kilobytes. 1 kilobyte = 1024 bytes. Therefore, 8 K = 8 * 1024 = 8192 bytes.
- To address each byte in the memory, we need a unique address. The number of unique addresses that can be generated with n address lines is 2^n. Therefore, we need 2^13 = 8192 unique addresses to address each byte in the memory.
- Hence, we need 13 address lines to generate these 8192 unique addresses.
- To read or write data from/to the memory, we need a data bus consisting of data lines. Since the memory has a capacity of 8192 bytes, we need 8 data lines to transfer 8 bits of data at a time (1 byte).
Free Test
FREE
Start Free Test
Start Free Test
Community Answer
How many separate address and data lines are needed for a memory of 8 ...
Required to address 8K of memory. We know that, 10 address bits allow the addressing of 1024 bytes (1K) of memory.
So, “1024” starts with “10”. Therefore, we need an additional 3 address bits to increase this by a factor of 8 (8 = 2 cubed), giving a total of 13 address bits.
Memory size = 8 K × 16 = 213 × 16
So, address line  = 13, data line = 16
Hence, the correct option is (B).
< Previous Question Next Question >
Explore Courses for Computer Science Engineering (CSE) exam

Similar Computer Science Engineering (CSE) Doubts

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 000400000, and a stack page starting at virtual address 0FFFFF000. The amount of memory required for storing the page tables of this process is

Top Courses for Computer Science Engineering (CSE)View all

Top Courses for Computer Science Engineering (CSE)

How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer?
Question Description
How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer? for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Question and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer? covers all topics & solutions for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer?.
Solutions for How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer? in English & in Hindi are available as part of our courses for Computer Science Engineering (CSE). Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free.
Here you can find the meaning of How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer? defined & explained in the simplest way possible. Besides giving the explanation of How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer?, a detailed solution for How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer? has been provided alongside types of How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer? theory, EduRev gives you an ample number of questions to practice How many separate address and data lines are needed for a memory of 8 K × 16 ?a)13 address, 3 data linesb)13 address, 16 data linesc)12 address, 4 data linesd)13 address, 4 data linesCorrect answer is option 'B'. Can you explain this answer? tests, examples and also practice Computer Science Engineering (CSE) tests.
Explore Courses for Computer Science Engineering (CSE) exam

Top Courses for Computer Science Engineering (CSE)

Explore Courses

Suggested Free Tests

Signup for Free!
Signup to see your scores go up within 7 days! Learn & Practice with 1000+ FREE Notes, Videos & Tests.
10M+ students study on EduRev
Get App
© EduRev
Education Revolution
Follow Us
Signup on EduRev and stay on top of your study goals
10M+ students crushing their study goals daily