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Electrical Engineering (EE) Exam > Electrical Engineering (EE) Notes > Analog and Digital Electronics > Previous Year Questions- BJT, FET and their Biasing Circuits - 1

Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Q: 1. What is the difference between BJT and FET in terms of operation?

Ans. BJT (Bipolar Junction Transistor) is a current-controlled device, meaning that the output current is controlled by the input current. It has three regions: emitter, base, and collector. FET (Field Effect Transistor), on the other hand, is a voltage-controlled device where the output current is controlled by the voltage applied to the gate terminal. FETs have three terminals: source, gate, and drain. This fundamental difference affects their applications and biasing requirements.

Q: 2. What are the common biasing techniques used for BJTs?

Ans. The common biasing techniques for BJTs include fixed bias, collector feedback bias, emitter bias, and voltage divider bias. Fixed bias uses a resistor connected to the base for biasing. Collector feedback bias uses a resistor from the collector to the base, providing stability. Emitter bias includes an emitter resistor for better temperature stability. Voltage divider bias employs two resistors to provide a stable base voltage, making it one of the most widely used techniques.

Q: 3. How does temperature affect the biasing of BJTs and FETs?

Ans. Temperature variations can significantly impact the biasing of BJTs and FETs. For BJTs, an increase in temperature leads to an increase in the saturation current, which can cause thermal runaway if not properly managed. FETs are less affected by temperature, but their threshold voltage can shift, impacting the biasing point. Hence, proper biasing techniques are crucial to maintain stability across temperature changes.

Q: 4. What is the significance of the Q-point in the biasing of transistors?

Ans. The Q-point, or Quiescent point, is the DC operating point of a transistor in the absence of an input signal. It is significant because it determines the linear region of operation for amplification. Properly setting the Q-point ensures that the transistor operates efficiently without distortion during signal amplification. Biasing circuits are designed to stabilize this Q-point against variations in temperature and transistor parameters.

Q: 5. What are the advantages of using FETs over BJTs in circuit design?

Ans. FETs offer several advantages over BJTs, including higher input impedance, which reduces loading effects on previous circuit stages. They also have lower noise levels and better thermal stability, making them suitable for high-frequency applications. Additionally, FETs are less susceptible to thermal runaway, and their voltage-controlled operation allows for simpler biasing circuits, enhancing overall circuit performance.

Q1: A BJT biasing circuit is shown in the figure, where V_BE = 0.7 V and β = 100. The Quiescent Point values of V_CE and I_C are respectively (2024)
(a) 4.6 V and 2.46 mA
(b) 3.5 V and 2.46 mA
(c) 2.61 V and 3.13 mA
(d) $4.6 V$ 4.6 V and 3.13 mA
Ans: (a)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) KVL in input loop,
4 − 33.33k × I_B − 0.7 − I_ER_E = 0
3.3 − 33.33k × I_B − (1+β)I_B × 1k = 0
I_C = βI_B = 100 × 24.56 × 10⁻⁶ = 2.46 mA
I_E = (1 + β)I_B = 2.47 mA
KVL in outer loop :
12 − 2k × I_C− V_CE− I_ER_E= 0
12 − V_CE = 2k × I_C+ I_E × 1k
12 − V_CE = 7.39 ⇒ V_CE = 4.61 V

Q2: All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true? (2023)
(a) When switch S is ON, both D₁and D₂ conducts and D₃ is reverse biased
(b) When switch S is ON, D₁conducts and both D₂ and D₃ are reverse biased
(c) When switch S is OF F, D₁ is reverse biased and both D₂and D₃conduct
(d) When switch S is OFF, D₁ conducts, D₂ is reverse biased and D₃ conducts
Ans: (b, c)
Sol: Case (i): Switch S is ON
Assume D₃→ OFF, D₂→ OFF and D₁→ ON
Redraw the circuit :
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) ∴ Our assumption is correct.
Case (ii) : Switch SS is OFF.
Then, D₃→ ON, D₂→ ON and D₁→ OFF
Redraw the circuit :
∴ Circuit satisfy this condition also.
Hence, option (B) and (C) will be correct.

Q3: In the BJT circuit shown, beta of the PNP transistor is 100. Assume V_BE= −0.7V. The voltage across R_c will be 5 V when R₂ is __________ kΩ.
(Round off to 2 decimal places.) (2021)
(a) 84.25
(b) 8.25
(c) 17.06
(d) 17.06
Ans: (c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) I_E = 1.53 mA
I_B = 0.0151 mA
−12 + 1.2k × 1.53 m + 0.7 + V_B = 0
V_B = 9.464 V
I_x + I_B = I_y
⇒ I_y= 0.5396 + 0.0151
I_y= 0.5546 mA
V_B = 0.5546 m x R₂= 9.464
R₂ = 17.06 kΩ

Q4: The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an uncharged condition, a bias of +3V is applied to the gate contact with respect to the body contact. The charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained within the dashed box shown, upon application of bias, expressed as a multiple of Q (absolute value in Coulombs, rounded off to the nearest integer) is __________ . (2020)
(a) 0
(b) 1
(c) -1
(d) 2
Ans: (a)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) Overall charge in side the box q + q − q − q = 0 charge

Q5: The enhancement type MOSFET in the circuit below operates according to the square law. μ_nC_ox = 100μA/V², the threshold voltage (V_T) is 500 mV. Ignore channel length modulation. The output voltage V_out is (2019)
(a) 100 mV
(b) 500 mV
(c) 600 mV
(d) 2 V
Ans: (c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) As, V_DS = V_GS
MOSFET is in saturation,
5×10⁻⁶ = (1/2) x 100 × 10⁻⁶× 10(V_GS−0.5)²
V_GS= 0.6
V₀ = 600 mV

Q6: Given, V_gs is the gate-source voltage, V_ds is the drain source voltage, and V_th is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are (2019)
(a) $V g s < V t h; V d s \geq V g s - V t h$ V_gs < V_th; V_ds ≥ V_gs − V_th
(b) V_gs > V_th; V_ds ≥ V_gs− V_th
(c) $V g s > V t h; V d s \leq V g s - V t h$ V_gs > V_th; V_ds ≤ V_gs − V_th
(d) $V g s < V t h; V d s \leq V g s - V t h$ V_gs < V_th; V_ds ≤ V_gs − V_th
Ans: (b)
Sol: For NMOS transistor to be in saturation the condition will be
V_gs> V_th
and V_ds ≥ V_gs − V_th

Q7: In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain β = 100. The base-emitter voltage drop is a constant, V_BE = 0.7 V. The value of the The venin equivalent resistance R_Th (in Ω) as shown in the figure is ______ (up to 2 decimal places). (2018)
(a) 70.45
(b) 85.25
(c) 90.09
(d) 105.65
Ans: (c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) To calculate R_Th D.C. volatage should be short circuited.
= 1kΩ∣∣99.0099
R_Th = 90.09Ω

Q8: For the circuit shown in the figure below, it is given that V_CE = V_CC/2. The transistor has β = 29 and V_BE = 0.7V when the B-E junction is forward biased.
For this circuit, the value of R_B/R is (SET-2 (2017))
(a) 43
(b) 92
(c) 121
(d) 129
Ans: (d)
Sol: In the input loop,
10 = (1+β)I_B× 4R + I_B× R_B+ 0.7 + (1+β)I_B× R
10 = 30I_B× 4R + I_B× R_B+ 0.7 + 30 × I_B × R
9.3 = 150 × I_B × R + I_B × R_B.....(i)
Ouput loop,
10 = (1+β)I_B × 4R + 5V + (1+β)I_B × R
5 = 30I_B × 4R + 30 × I_B × R
5 = 150 × I_B × R.....(ii)
using equation (i) and (ii),
I_BR_B = 9.3−5 = 4.3
and simultaneously putting value of I_BR from equation (ii) in equation (i),
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)
Q9: The circuit shown in the figure uses matched transistors with a thermal voltage V_T = 25mV. The base currents of the transistors are negligible. The value of the resistance R in kΩ that is required to provide 1 μA bias current for the differential amplifier block shown is ______. (SET-1(2017))
(a) 25.4
(b) 50.5
(c) 172.7
(d) 256.4
Ans: (c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) V_BE1= V_BE2 + I₀R
I₀R = V_BE1− V_BE2= V_Iln(I_R/I₃) − V_Tln(I₀/I₃)
where, I_s→ Reverse saturation current

Q10: A transistor circuit is given below. The Zener diode breakdown voltage is 5.3 V as shown. Take base to emitter voltage drop to be 0.6 V. The value of the current gain β is _________. (SET-1 (2016))
(a) 2.7
(b) 12
(c) 19
(d) 28
Ans: (c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) V_B= 5.3V
V_E = V_B− 0.6 = 4.7V
I_B= I₁− I₂ = 0.5mA
I_E/I_B = β + 1 = 20
β = 19

Q11: When a bipolar junction transistor is operating in the saturation mode, which one of the following statements is TRUE about the state of its collector-base (CB) and the base-emitter (BE) junctions? (SET-2(2015))
(a) The CB junction is forward biased and the BE junction is reverse biased.
(b) The CB junction is reverse biased and the BE junction is forward biased.
(c) Both the CB and BE junctions are forward biased.
(d) Both the CB and BE junctions are reverse biased.
Ans: (c)

Q12: In the following circuit, the transistor is in active mode and V_C = 2 V. To get V_C = 4 V, we replace R_C with R_C′ . Then the ratio R_C′/R_C is ______. (SET-2 (2015))
(a) 0.5
(b) 0.75
(c) 1
(d) 1.25
Ans: (b)
Sol: CASE-I:
V_C= 2V
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) CASE-II
when V_C = 4V
R_C → R_C′
From above equation (iii) and (i),

Q13: In the given circuit, the silicon transistor has β = 75 and a collector voltage V_c = 9 V. Then the ratio of R_B and R_C is ________. (SET-1 (2015))
(a) 75.25
(b) 105.13
(c) 150.36
(d) 175.45
Ans: (b)
Sol: Consider the circuit shown in figure.
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) V_C = 9V
So, (15-9)/R_C= I_E

Q14: The transistor in the given circuit should always be in active region. Take V_CE(sat)= 0.2V, V_BE = 0.7 V. The maximum value of R_cin Ω which can be used, is _____. (SET-2 (2014))
(a) 8.63
(b) 10.12
(c) 22.32
(d) 30.48
Ans: (c)
Sol: In input loop:
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) So, I_c = β × I_b = 100 × 2.15mA
= 0.215A
Now KVL in output loop:
V_CE = 5 − 0.215RC
For active region V_CE > 0.2V
⇒ 0.215R_C < 5 − 0.2
⇒ R_Cmax = 4.8/0.215 ≃ 22.32Ω

Q15: The voltage gain A_vof the circuit shown below is (2012)
(a) ∣A_v∣ ≈ 200
(b) ∣A_v∣ ≈ 100
(c) ∣A_v∣ ≈ 20
(d) $∣ A v ∣ \approx 10$ ∣A_v∣ ≈ 10
Ans: (d)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) Equivalent A.C. model will be taking,
h_ie = 1kΩ
h_fe = β = 100

Q16: The transistor circuit shown uses a silicon transistor with V_B_E = 0.7V, I_C≈ I_E and a dc current gain of 100. The value of V₀ is (2010)
(a) 4.65
(b) 5
(c) 6.3
(d) 7.23
Ans: (a)
Sol: KVL⇒
10 = 10kI_b+ 0.7 + (100)(I_b)100
I_b = 9.3/20k = 0.465mA
V_o= 100 × 0.465 × 100 = 4.65V

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FAQs on Previous Year Questions- BJT, FET and their Biasing Circuits - 1 - Analog and Digital Electronics - Electrical Engineering (EE)

1. What is the difference between BJT and FET in terms of operation?

Ans. BJT (Bipolar Junction Transistor) is a current-controlled device, meaning that the output current is controlled by the input current. It has three regions: emitter, base, and collector. FET (Field Effect Transistor), on the other hand, is a voltage-controlled device where the output current is controlled by the voltage applied to the gate terminal. FETs have three terminals: source, gate, and drain. This fundamental difference affects their applications and biasing requirements.

2. What are the common biasing techniques used for BJTs?

Ans. The common biasing techniques for BJTs include fixed bias, collector feedback bias, emitter bias, and voltage divider bias. Fixed bias uses a resistor connected to the base for biasing. Collector feedback bias uses a resistor from the collector to the base, providing stability. Emitter bias includes an emitter resistor for better temperature stability. Voltage divider bias employs two resistors to provide a stable base voltage, making it one of the most widely used techniques.

3. How does temperature affect the biasing of BJTs and FETs?

Ans. Temperature variations can significantly impact the biasing of BJTs and FETs. For BJTs, an increase in temperature leads to an increase in the saturation current, which can cause thermal runaway if not properly managed. FETs are less affected by temperature, but their threshold voltage can shift, impacting the biasing point. Hence, proper biasing techniques are crucial to maintain stability across temperature changes.

4. What is the significance of the Q-point in the biasing of transistors?

Ans. The Q-point, or Quiescent point, is the DC operating point of a transistor in the absence of an input signal. It is significant because it determines the linear region of operation for amplification. Properly setting the Q-point ensures that the transistor operates efficiently without distortion during signal amplification. Biasing circuits are designed to stabilize this Q-point against variations in temperature and transistor parameters.

5. What are the advantages of using FETs over BJTs in circuit design?

Ans. FETs offer several advantages over BJTs, including higher input impedance, which reduces loading effects on previous circuit stages. They also have lower noise levels and better thermal stability, making them suitable for high-frequency applications. Additionally, FETs are less susceptible to thermal runaway, and their voltage-controlled operation allows for simpler biasing circuits, enhancing overall circuit performance.

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