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Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Q1: A BJT biasing circuit is shown in the figure, where VBE = 0.7 V and β = 100. The Quiescent Point values of VCE and  IC are respectively (2024)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 4.6 V and 2.46 mA
(b) 3.5 V and 2.46 mA
(c) 2.61 V and 3.13 mA
(d) 4.6 V4.6 V and 3.13 mA
Ans: 
(a)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)KVL in input loop,
4 − 33.33k × IB − 0.7 − IERE = 0
3.3 − 33.33k × IB − (1+β)IB × 1k = 0
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)IC = βIB = 100 × 24.56 × 10−6 = 2.46 mA
IE = (1 + β)IB = 2.47 mA
KVL in outer loop :
12 − 2k × I− VCE − IER= 0  
12 − VCE = 2k × I+ IE × 1k
 12 − VCE = 7.39 ⇒ VCE = 4.61 V

Q2: All the elements in the circuit shown in the following figure are ideal. Which of the following statements is/are true? (2023)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) When switch S is ON, both Dand D2 conducts and D3 is reverse biased
(b) When switch S is ON, Dconducts and both D2 and D3 are reverse biased  
(c) When switch S is OF F, D1 is reverse biased and both Dand Dconduct
(d) When switch S is OFF, D1 conducts, D2 is reverse biased and D3 conducts  
Ans:
(b, c)
Sol: Case (i): Switch S is ON
Assume D→ OFF, D→ OFF and D→ ON
Redraw the circuit :
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)∴ Our assumption is correct.
Case (ii) : Switch SS is OFF.
Then, D→ ON, D→ ON and D→ OFF
Redraw the circuit :
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)∴ Circuit satisfy this condition also.
Hence, option (B) and (C) will be correct.

Q3: In the BJT circuit shown, beta of the PNP transistor is 100. Assume VBE = −0.7V.  The voltage across Rc will be 5 V when R2 is __________  kΩ.
(Round off to 2 decimal places.)  (2021)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 84.25
(b) 8.25
(c) 17.06
(d) 17.06
Ans:
(c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)IE = 1.53 mA
IB = 0.0151 mA
−12 + 1.2k × 1.53 m + 0.7 + VB = 0
VB = 9.464 V
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Ix + IB = Iy
⇒ I= 0.5396 + 0.0151
I= 0.5546 mA
VB = 0.5546 m x R= 9.464
R2 = 17.06 kΩ

Q4: The cross-section of a metal-oxide-semiconductor structure is shown schematically. Starting from an uncharged condition, a bias of +3V is applied to the gate contact with respect to the body contact. The charge inside the silicon dioxide layer is then measured to be +Q. The total charge contained within the dashed box shown, upon application of bias, expressed as a multiple of Q (absolute value in Coulombs, rounded off to the nearest integer) is __________ . (2020)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 0
(b) 1
(c) -1
(d) 2
Ans: 
(a)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Overall charge in side the box q + q − q − q = 0 charge

Q5: The enhancement type MOSFET in the circuit below operates according to the square law. μnCox = 100μA/V2, the threshold voltage (VT) is 500 mV. Ignore channel length modulation. The output voltage Vout is  (2019)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 100 mV
(b) 500 mV
(c) 600 mV
(d) 2 V
Ans:
(c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)As, VDS = VGS
MOSFET is in saturation,
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)5×10−6 = (1/2)  x 100 × 10−6 × 10(VGS−0.5)2 
VGS = 0.6
V0 = 600 mV

Q6: Given, Vgs is the gate-source voltage, Vds is the drain source voltage, and Vth is the threshold voltage of an enhancement type NMOS transistor, the conditions for transistor to be biased in saturation are (2019)
(a) Vgs<Vth;VdsVgsVthVgs < Vth; Vds ≥ Vgs − Vth
(b) Vgs > Vth; Vds ≥ Vgs − Vth
(c) Vgs>Vth;VdsVgsVthVgs > Vth; Vds ≤ Vgs − Vth
(d) Vgs<Vth;VdsVgsVthVgs < Vth; Vds ≤ Vgs − Vth
Ans: 
(b)
Sol: For NMOS transistor to be in saturation the condition will be
Vgs > Vth
and Vds ≥ Vgs − Vth

Q7: In the circuit shown in the figure, the bipolar junction transistor (BJT) has a current gain β = 100. The base-emitter voltage drop is a constant, VBE = 0.7 V. The value of the The venin equivalent resistance RTh (in Ω) as shown in the figure is ______ (up to 2 decimal places). (2018)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 70.45
(b) 85.25
(c) 90.09
(d) 105.65
Ans:
(c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)To calculate RTh D.C. volatage should be short circuited.
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)= 1kΩ∣∣99.0099
RTh = 90.09Ω

Q8: For the circuit shown in the figure below, it is given that VCE = VCC/2. The transistor has β = 29 and VBE = 0.7V when the B-E junction is forward biased.
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)For this circuit, the value of RB/R is (SET-2  (2017))
(a) 43
(b) 92
(c) 121
(d) 129
Ans: 
(d)
Sol: In the input loop,
10 = (1+β)I× 4R + I× R+ 0.7 + (1+β)I× R
10 = 30I× 4R + I× R+ 0.7 + 30 × IB × R
9.3 = 150 × IB × R + IB × RB.....(i)
Ouput loop,
10 = (1+β)IB × 4R + 5V + (1+β)IB × R
5 = 30IB × 4R + 30 × IB × R
5 = 150 × IB × R.....(ii)  
using equation (i) and (ii),
IBRB = 9.3−5 = 4.3
and simultaneously putting value of IBR from equation (ii) in equation (i),
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)
Q9: The circuit shown in the figure uses matched transistors with a thermal voltage VT = 25mV. The base currents of the transistors are negligible. The value of the resistance R in kΩ that is required to provide 1 μA bias current for the differential amplifier block shown is ______. (SET-1(2017))
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 25.4
(b) 50.5
(c) 172.7  
(d) 256.4
Ans:
(c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)VBE1 = VBE2 + I0R
I0R = VBE1 − VBE2 = VIln(IR/I3) − VTln(I0/I3)
where, I→ Reverse saturation current
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)
Q10: A transistor circuit is given below. The Zener diode breakdown voltage is 5.3 V as shown. Take base to emitter voltage drop to be 0.6 V. The value of the current gain β is _________. (SET-1 (2016))
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 2.7
(b) 12
(c) 19
(d) 28
Ans: 
(c)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)V= 5.3V
VE = V− 0.6 = 4.7V
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)I= I− I2 = 0.5mA  
IE/IB = β + 1 = 20
 β = 19

Q11: When a bipolar junction transistor is operating in the saturation mode, which one of the following statements is TRUE about the state of its collector-base (CB) and the base-emitter (BE) junctions? (SET-2(2015))
(a) The CB junction is forward biased and the BE junction is reverse biased.
(b) The CB junction is reverse biased and the BE junction is forward biased.
(c) Both the CB and BE junctions are forward biased.
(d) Both the CB and BE junctions are reverse biased.
Ans: 
(c)

Q12: In the following circuit, the transistor is in active mode and VC = 2 V. To get VC = 4 V, we replace RC with RC′ . Then the ratio  RC′/RC is ______. (SET-2 (2015))
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 0.5
(b) 0.75
(c) 1
(d) 1.25
Ans: 
(b)
Sol: CASE-I:
V= 2V
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)CASE-II
when  VC = 4V
RC → RC
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)From above equation (iii) and (i),
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)
Q13: In the given circuit, the silicon transistor has β = 75 and a collector voltage Vc = 9 V. Then the ratio of RB and RC is ________. (SET-1 (2015))
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 75.25
(b) 105.13
(c) 150.36
(d) 175.45
Ans:
(b)
Sol: Consider the circuit shown in figure.
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)VC = 9V  
So, (15-9)/R= IE
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)
Q14: The transistor in the given circuit should always be in active region. Take VCE(sat) = 0.2V, VBE = 0.7 V. The maximum value of  Rin Ω which can be used, is _____. (SET-2 (2014))
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) (a) 8.63
(b) 10.12
(c) 22.32
(d) 30.48
Ans:
(c)
Sol: In input loop:
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)So, Ic = β × Ib = 100 × 2.15mA
= 0.215A
Now KVL in output loop:
VCE = 5 − 0.215RC
For active region VCE > 0.2V
⇒ 0.215RC < 5 − 0.2
⇒ RCmax = 4.8/0.215 ≃ 22.32Ω

Q15: The voltage gain Aof the circuit shown below is (2012)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) ∣Av∣ ≈ 200
(b) ∣Av∣ ≈ 100
(c) ∣Av∣ ≈ 20
(d) Av10∣Av∣ ≈ 10
Ans:
(d)
Sol: Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Equivalent A.C. model will be taking,
hie = 1kΩ
hfe = β = 100
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)
Q16: The transistor circuit shown uses a silicon transistor with VBE = 0.7V, I≈ IE and a dc current gain of 100. The value of V0 is  (2010)
Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE)(a) 4.65
(b) 5
(c) 6.3
(d) 7.23
Ans:
(a)
Sol: KVL⇒
10 = 10kI+ 0.7 + (100)(Ib)100
Ib = 9.3/20k = 0.465mA
V= 100 × 0.465 × 100 = 4.65V 

The document Previous Year Questions- BJT, FET and their Biasing Circuits - 1 | Analog and Digital Electronics - Electrical Engineering (EE) is a part of the Electrical Engineering (EE) Course Analog and Digital Electronics.
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FAQs on Previous Year Questions- BJT, FET and their Biasing Circuits - 1 - Analog and Digital Electronics - Electrical Engineering (EE)

1. What is the difference between BJT and FET in terms of operation?
Ans. BJT (Bipolar Junction Transistor) is a current-controlled device, meaning that the output current is controlled by the input current. It has three regions: emitter, base, and collector. FET (Field Effect Transistor), on the other hand, is a voltage-controlled device where the output current is controlled by the voltage applied to the gate terminal. FETs have three terminals: source, gate, and drain. This fundamental difference affects their applications and biasing requirements.
2. What are the common biasing techniques used for BJTs?
Ans. The common biasing techniques for BJTs include fixed bias, collector feedback bias, emitter bias, and voltage divider bias. Fixed bias uses a resistor connected to the base for biasing. Collector feedback bias uses a resistor from the collector to the base, providing stability. Emitter bias includes an emitter resistor for better temperature stability. Voltage divider bias employs two resistors to provide a stable base voltage, making it one of the most widely used techniques.
3. How does temperature affect the biasing of BJTs and FETs?
Ans. Temperature variations can significantly impact the biasing of BJTs and FETs. For BJTs, an increase in temperature leads to an increase in the saturation current, which can cause thermal runaway if not properly managed. FETs are less affected by temperature, but their threshold voltage can shift, impacting the biasing point. Hence, proper biasing techniques are crucial to maintain stability across temperature changes.
4. What is the significance of the Q-point in the biasing of transistors?
Ans. The Q-point, or Quiescent point, is the DC operating point of a transistor in the absence of an input signal. It is significant because it determines the linear region of operation for amplification. Properly setting the Q-point ensures that the transistor operates efficiently without distortion during signal amplification. Biasing circuits are designed to stabilize this Q-point against variations in temperature and transistor parameters.
5. What are the advantages of using FETs over BJTs in circuit design?
Ans. FETs offer several advantages over BJTs, including higher input impedance, which reduces loading effects on previous circuit stages. They also have lower noise levels and better thermal stability, making them suitable for high-frequency applications. Additionally, FETs are less susceptible to thermal runaway, and their voltage-controlled operation allows for simpler biasing circuits, enhancing overall circuit performance.
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