The size of the physical address space of a processor is 2Pbytes. The word length is 2Wbytes. The capacity of cache memory is 2Nbytes. The size of each cache block is 2Mwords. For a K-way set-associative cache memory, the length (in number of bits) of the tag field isa)P andminus; N andminus; log2Kb)P andminus; N + log2Kc)P andminus; N andminus; M andminus; W andminus; log2Kd)P andminus; N andminus; M andminus; W + log2KCorrect answer is option 'B'. Can you explain this answer? - EduRev Computer Science Engineering (CSE) Question

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The size of the physical address space of a processor is 2^P bytes. The word length is 2^W bytes. The capacity of cache memory is 2^N bytes. The size of each cache block is 2^M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is

a)
P − N − log₂K
b)
P − N + log₂K
c)
P − N − M − W − log₂K
d)
P − N − M − W + log₂K

Correct answer is option 'B'. Can you explain this answer?

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The size of the physical address space of a processor is 2Pbytes. The ...

Physical Address Space = 2^P Bytes. Word Length is 2^W bytes, which means each word is of size 2^W bytes. Cache memory size = 2^N Bytes and Tag Size = 2^X Bytes. Physical address is P - W bits Number of blocks in cache = 2^(N-W-M) It is a K-way set associative cache memory, each set in cache will have K-blocks. So, Number of sets = 2^(N-W-M)/ K SET bits will be N-W-M-logk Offset bits will be M We know, TAG bits = Main memory bits - SET bits - offset bits So, TAG bits(x) = P - W - (N-M-W-logk)- M = P - W - N + M + W + logk - M x = P - N + logk Option (B) is Correct.

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The size of the physical address space of a processor is 2Pbytes. The word length is 2Wbytes. The capacity of cache memory is 2Nbytes. The size of each cache block is 2Mwords. For a K-way set-associative cache memory, the length (in number of bits) of the tag field isa)P − N − log2Kb)P − N + log2Kc)P − N − M − W − log2Kd)P − N − M − W + log2KCorrect answer is option 'B'. Can you explain this answer?

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