**Positive-Edge-Triggered JK Flip-Flop**

A positive-edge-triggered JK flip-flop is a type of sequential logic circuit that stores and outputs a single bit of information. It is called positive-edge-triggered because it only responds to changes in the input signals when the clock signal transitions from low to high (i.e., rising edge).

**JK Flip-Flop Truth Table**

The truth table for a positive-edge-triggered JK flip-flop is as follows:

```
Clock (CLK) J K Q(t) Q(t+1)
-----------------------------------
0 X X Q Q
1 0 0 Q Q
1 0 1 Q 0
1 1 0 Q 1
1 1 1 Q ~Q
```

Where:
- CLK represents the clock input
- J represents the J input
- K represents the K input
- Q(t) represents the current state of the flip-flop output
- Q(t+1) represents the next state of the flip-flop output

**Effect of Low J and Low K Inputs**

When both J and K inputs of a positive-edge-triggered JK flip-flop are low, the flip-flop enters an inactive state. This means that the output state (Q) remains unchanged regardless of the clock signal.

- When CLK = 0 (low), the output (Q) remains the same as the previous state.
- When CLK = 1 (rising edge), the output (Q) remains the same as the previous state.

**Effect of High J and Low K Inputs on Rising Edge of Clock**

When the J input is high and the K input is low, the flip-flop enters a toggle state. This means that the output state (Q) toggles between 1 and 0 on the rising edge of the clock.

- When CLK = 0 (low), the output (Q) remains the same as the previous state.
- When CLK = 1 (rising edge), the output (Q) toggles between 1 and 0. If the previous state was 1, the next state will be 0. If the previous state was 0, the next state will be 1.

Therefore, the correct answer is option D: Inactive state for low J and low K inputs, and toggle state for high J and low K inputs on the rising edge of the clock.

Here inactive state means no change output same as previous stateAnd after clock is applied then it became toggle that is changes it present state to current state