A 5 stage pipelined processor has IF, ID, EXE, MEM and WB. WB stage operation is divided into two parts. In the first part register write operation and in the second part register read operation is performed. The latencies of all those stages are 300, 400, 500, 500 and 300 (in nano second) respectively. Consider the following code is executed on this processorFind minimum number of nop instructions (no operation) to eliminate hazards without using operans forwarding. (Assume each instruction takes one cycle to complete its operation in every stage)Correct answer is '4'. Can you explain this answer?

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Find minimum number of nop instructions (no operation) to eliminate hazards without using operans forwarding. (Assume each instruction takes one cycle to complete its operation in every stage)

Correct answer is '4'. Can you explain this answer?

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A 5 stage pipelined processor has IF, ID, EXE, MEM and WB. WB stage op...

Since I₁ and I₂ are dependent. So I₂ will enter into execute stage when I₁completes WB stage.It creates 2 nop. Similarly I₃ and I₄ are dependent. They create 2 nop.
Total 4 nop instructions are required to eliminate hazards.

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A 5 stage pipelined processor has IF, ID, EXE, MEM and WB. WB stage operation is divided into two parts. In the first part register write operation and in the second part register read operation is performed. The latencies of all those stages are 300, 400, 500, 500 and 300 (in nano second) respectively. Consider the following code is executed on this processorFind minimum number of nop instructions (no operation) to eliminate hazards without using operans forwarding. (Assume each instruction takes one cycle to complete its operation in every stage)Correct answer is '4'. Can you explain this answer?

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